Stacked Semiconductor Package With Conductive Frame for Dual-Side Cooling
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Solution Overview
Problem
Legacy dual side heat dissipation solutions for semiconductor packages face challenges such as low chip density, high thermal resistance, and complex assembly processes, which hinder the miniaturization and high integration of electronic devices.
Innovation Solution
A semiconductor package design featuring a chip interconnect component with an electrically conductive frame connecting two chips on both sides, along with an insulating material filling the gap between them, allowing for balanced dual side heat dissipation and increased chip density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a single or dual side heat dissipation solution is used with power semiconductor chips on an insulating substrate, then heat dissipation is achieved, but chip density is low and thermal resistance is high
Solution Approach 1:
The patent transitions from planar single-sided or dual-sided heat dissipation to three-dimensional stacked chip architecture. Multiple power semiconductor chips are vertically stacked and connected through conductive pillars, enabling heat to be dissipated from multiple surfaces simultaneously. This spatial dimensionality change increases chip density while maintaining effective thermal pathways through the stacked structure.
Solution Approach 2:
The heat dissipation function is segmented across multiple independent chips stacked vertically. Each chip has its own heat dissipation pathways through conductive pillars to heat dissipation substrates, allowing parallel heat dissipation from multiple sources rather than a single centralized path, thereby reducing overall thermal resistance.
2Temperature
If a single or dual side heat dissipation solution is used with power semiconductor chips on an insulating substrate, then heat dissipation is achieved, but thermal resistance is high
Solution Approach 1:
By stacking chips vertically and providing heat dissipation substrates on multiple levels, the patent creates three-dimensional thermal pathways. Heat can escape from the top, bottom, and lateral surfaces of the stacked structure, significantly reducing thermal resistance compared to planar configurations where heat must travel longer distances to reach dissipation surfaces.
Solution Approach 2:
Conductive pillars serve as intermediary thermal pathways between the power semiconductor chips and heat dissipation substrates. These pillars provide direct, low-resistance thermal coupling, efficiently transferring heat from each chip to dedicated heat dissipation surfaces without relying on high-resistance interfaces.
3Temperature
If a single or dual side heat dissipation solution is used, then heat dissipation is achieved, but the assembling process is complicated
Solution Approach 1:
The conductive pillars and heat dissipation substrates are pre-integrated into a unified package structure before chip mounting. This preliminary preparation of thermal pathways simplifies the subsequent chip stacking process, as the thermal management infrastructure is already in place rather than requiring complex post-assembly thermal interface installations.
Solution Approach 2:
The patent merges electrical interconnection and thermal management functions into a single integrated package structure. The conductive pillars simultaneously provide electrical connectivity between stacked chips and serve as thermal pathways to heat dissipation substrates, eliminating the need for separate thermal interface materials and simplifying the overall assembly process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances heat dissipation performance, increases chip density, and simplifies the assembly process by balancing thermal paths and reducing the number of components, thereby addressing the limitations of legacy solutions.
Implementation Method 1
one side of the electrically conductive frame is electrically connected to the second surface of the first chip, and the other side of the electrically conductive frame is electrically connected to the third surface of the second chip
Implementation Method 2
an insulating material for filling a gap of the electrically conductive frame between the first chip and the second chip
Data Source
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AI summary
Embodiments of the present disclosure relate to a semiconductor package, a package forming method, and a power supply module. For example, a semiconductor package is provided. The semiconductor package may include a first chip comprising a first surface, and a second surface opposite the first surface. The semiconductor package may also include a chip interconnect component located on the second surface of the first chip. In addition, the semiconductor package may include a second chip located on the chip interconnect component, comprising a third surface in contact with the chip interconnect component, and a fourth surface opposite the third surface. The chip interconnect component comprises an electrically conductive frame, one side of the electrically conductive frame is electrically connected to the second surface of the first chip, and the other side of the electrically conductive frame is electrically connected to the third surface of the second chip. The chip interconnect component may further comprise an insulating material for filling a gap of the electrically conductive frame between the first chip and the second chip. By arranging at least two chip on both sides of a preformed chip interconnect component, embodiments of the present disclosure achieve a high density chip layout for a 3D structure.