Stacked Chip Package via Holes and Anisotropic Conductive Film
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor device architectures face challenges with increased complexity and size due to multiple central processing units (CPUs) requiring expanded motherboard space, timing synchronization issues, and inadequate heat dissipation, especially when stacking integrated chips.
Innovation Solution
A semiconductor device design featuring glass substrates with via holes and anisotropic conductive films for chip-on-glass bonding, allowing for stacked chip integration with enhanced heat dissipation and reduced packaging dimensions by using a trench layout and conductive bumps for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple integrated chips are stacked to reduce packaging size, then packaging dimension is reduced, but heat dissipation becomes inadequate
Solution Approach 1:
The patent utilizes the anisotropic conductive film's ability to flow into via holes, creating a porous-like structure that facilitates heat dissipation. The via holes act as channels for heat removal while maintaining the compact stacked configuration, resolving the contradiction between reduced packaging volume and adequate heat dissipation.
2Reliability
If anisotropic conductive film is applied for chip bonding, then electrical connection is achieved, but uneven film distribution and bubble formation occur
Solution Approach 1:
The patent extracts the excess anisotropic conductive film into via holes, removing the harmful effect of uneven film distribution and bubble formation. This allows the bonding process to proceed with relaxed film application control while maintaining reliable electrical connections.
3Productivity
If multiple CPUs are distributed on motherboard to meet processing needs, then processing capacity is enhanced, but motherboard size and circuit complexity increase
Solution Approach 1:
The patent transitions from a two-dimensional distributed CPU architecture on the motherboard to a three-dimensional stacked chip architecture. By stacking chips vertically and using via holes for inter-layer connections, the system achieves enhanced processing capacity while reducing motherboard space requirements and simplifying circuit layout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design simplifies circuit layout, ensures consistent timing synchronization, reduces packaging size, and improves heat dissipation by allowing the anisotropic conductive film to flow into via holes, addressing issues of uneven film distribution and bubble formation.
Implementation Method 1
a first anisotropic conductive film deployed around the first device conductive bumps and the first substrate connectors, and flowing into the first via hole
Implementation Method 2
improves heat dissipation by allowing the anisotropic conductive film to flow into via holes
Data Source
AI summary
The present invention provides a semiconductor device including a first glass substrate, a first integrated chip, a first anisotropic conductive film, a second glass substrate, a second integrated chip, a second anisotropic conductive film, and a packaging body.