Stacked Semiconductor Chip Package With Through-Electrode Hybrid Bonding
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Solution Overview
Problem
Current semiconductor packaging techniques fail to efficiently integrate multiple high-performance semiconductor chips in a small, high-frequency signal processing package with excellent electrical characteristics and flexible chip arrangement.
Innovation Solution
A semiconductor package design featuring stacked semiconductor chips with vertically penetrating through electrodes and pads of varying widths, allowing for intermetallic hybrid bonding and flexible chip arrangement, including a zigzag configuration, to enhance electrical connectivity and packaging efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are integrated in a single package, then the functionality and performance are improved, but the packaging complexity and difficulty of achieving excellent electrical characteristics increase
Solution Approach 1:
The package is divided into multiple semiconductor chips, each functioning as an independent module with its own through electrodes and pads. This segmentation allows each chip to be optimized independently while contributing to the overall system functionality, resolving the contradiction between enhanced adaptability and increased packaging complexity.
Solution Approach 2:
Multiple semiconductor chips are stacked vertically in a nested configuration, with upper chips positioned on lower chips. This nesting approach maximizes the use of vertical space, enabling multiple functional modules to be integrated in a compact volume while maintaining manageable packaging complexity through systematic arrangement.
2Volume of moving object
If the size of the package is reduced, then the portability and integration density are improved, but the electrical characteristics for high-frequency signals deteriorate
Solution Approach 1:
The design transitions from a planar two-dimensional layout to a three-dimensional stacked configuration. By utilizing the vertical dimension, the package achieves high integration density and compact volume while maintaining excellent electrical characteristics through direct vertical interconnections via through electrodes, avoiding the signal integrity issues associated with horizontal routing in miniaturized packages.
Solution Approach 2:
The through electrode structure is replicated in each semiconductor chip, creating consistent vertical interconnection pathways throughout the stack. This copying of the electrode-pad configuration across multiple chips ensures uniform electrical characteristics and high-frequency signal performance regardless of package size reduction.
3Area of moving object
If through electrodes are positioned close together, then the chip area is reduced, but the manufacturing precision and alignment difficulty increase
Solution Approach 1:
The design employs asymmetric pad width configuration, where upper pads are wider than lower pads. This asymmetry creates a tapered connection structure that compensates for potential alignment variations, making the system more tolerant to manufacturing precision limitations while maintaining compact chip area through optimized spacing.
Solution Approach 2:
The pad width parameter is varied between upper and lower levels, with upper pads designed wider than lower pads. This parameter change creates a forgiving interface that accommodates alignment tolerances, enabling closer through electrode positioning and reduced chip area without proportionally increasing manufacturing difficulty.
4Adaptability or versatility
If pads of varying widths are used, then the flexibility in chip arrangement is improved, but the manufacturing complexity increases
Solution Approach 1:
Different pad widths are applied locally at different levels of the stack, with upper pads wider than lower pads. This local quality variation provides flexibility in chip arrangement and alignment tolerance without requiring complete redesign of the entire manufacturing process, as the asymmetric configuration can be integrated into existing fabrication workflows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables improved electrical connectivity and increased flexibility in chip arrangement, leading to enhanced packaging efficiency and productivity while maintaining excellent electrical characteristics, suitable for high-frequency signal processing.
Implementation Method 1
a first through electrode vertically penetrating the first semiconductor substrate... electrically connected to the first through electrode
Implementation Method 2
an upper protective layer at least partially surrounding the first upper pad... a lower protective layer at least partially surrounding the second lower pad
Data Source
AI summary
A semiconductor package includes a lower semiconductor chip, a first semiconductor chip, a first through-electrode vertically penetrating the first semiconductor substrate, a first upper pad connected to the first through electrode, a first circuit layer disposed on the lower surface of the first semiconductor substrate, and a first lower pad disposed on a lower surface of the first circuit layer. A second semiconductor chip includes a second through-electrode spaced apart from the first through-electrode and vertically penetrating the second semiconductor substrate. A second upper pad is connected to the second through electrode. A second circuit layer is disposed on the lower surface of the second semiconductor substrate, and a second lower pad is connected to the second through-electrode on the lower surface of the second circuit layer through the second circuit layer and is integrally formed with the first upper pad.