3D Stacked Semiconductor Chip ID Routing for Accurate Data Selection
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Solution Overview
Problem
The challenge of ensuring accurate data transmission in three-dimensional stack structures of semiconductor chips, particularly in minimizing the complexity of assigning stack IDs and ensuring data is transmitted to each chip in a three-dimensional stack structure.
Innovation Solution
A semiconductor chip design featuring symmetrically distributed ID transmission paths and decoding circuits that generate data selection signals, allowing accurate data transmission to corresponding internal receiving circuits, reducing the complexity of assigning stack IDs by using odd and even flag bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional stack structure is used to increase packaging density, then packaging capacity is improved, but data transmission accuracy deteriorates
Solution Approach 1:
The patent segments the ID transmission function into two separate symmetric paths (first ID transmission path and second ID transmission path) that are mirror-symmetrically distributed around the central axis. This segmentation allows independent signal routing while maintaining symmetry, thereby improving data transmission accuracy in three-dimensional stack structures while preserving increased packaging capacity.
Solution Approach 2:
The patent employs symmetric asymmetry by creating two ID transmission paths that are mirror-symmetric to each other but asymmetric relative to the central axis. This approach resolves the contradiction by providing redundant symmetric pathways that enhance reliability without compromising the three-dimensional stacking density.
2Reliability
If traditional ID transmission method is used, then device complexity is low, but data transmission accuracy to multiple chips deteriorates
Solution Approach 1:
The patent introduces mirror-symmetric ID transmission paths that are asymmetric relative to the central axis, creating a balanced yet differentiated routing structure. This allows accurate data transmission to multiple stacked chips while maintaining manageable device complexity through systematic symmetry rather than arbitrary complexity.
Solution Approach 2:
The patent transitions from a single-dimensional ID transmission approach to a two-dimensional symmetric routing architecture by distributing ID transmission paths on opposite sides of the central axis. This dimensional expansion enables accurate addressing of multiple chips in the stack while organizing complexity in a structured, manageable manner.
3Ease of operation
If stack ID assignment complexity is reduced, then ease of operation is improved, but data transmission reliability may deteriorate
Solution Approach 1:
The patent segments the ID transmission function into two independent but symmetric paths, allowing simplified ID assignment through odd-even flag bit differentiation while maintaining reliable data transmission. Each path can be independently managed, reducing operational complexity without compromising reliability.
Solution Approach 2:
By using mirror-symmetric paths with asymmetric positioning relative to the central axis, the patent enables simplified ID assignment procedures (odd/even differentiation) while the symmetric redundancy ensures data transmission reliability is maintained across multiple stacked chips.
Data Source
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AI summary
Embodiment of the present disclosure discloses a semiconductor chip, a semiconductor structure, and a semiconductor device. The semiconductor chip includes: a first ID transmission path, penetrating through a substrate of the semiconductor chip in a direction perpendicular to an active surface of the semiconductor chip; a second ID transmission channel, penetrating through the substrate in the direction perpendicular to the active surface of the semiconductor chip, and symmetrically distributed with the first ID transmission path based on a central axis of the semiconductor chip, where the central axis passes through a center of the semiconductor chip and is parallel to the active surface; and an ID decoding circuit, coupled to the first ID transmission path or the second ID transmission path, where the ID decoding circuit is configured to receive an ID signal and decode the ID signal to generate a data selection signal, where the semiconductor chip outputs data signals transmitted in a plurality of data transmission paths to corresponding internal receiving circuits respectively according to the data selection signal.