Stacked Chip Image Sensor Bottom Light-Sensitive Circuit Shielding
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Solution Overview
Problem
Conventional image sensors with light-sensitive circuit elements face issues with light-induced leakage, which can degrade performance, especially when these elements are not adequately shielded, leading to undesirable effects such as motion-related artifacts and reduced image quality.
Innovation Solution
A stacked chip formation is employed, where the light-sensitive circuit elements are positioned on the bottom chip, naturally shielded from light, eliminating the need for a dedicated photo-shield and allowing for effective light shielding without obstructing the light path to the photodetectors, and incorporating a random access memory network for flexible signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If light-sensitive circuit elements are positioned on the top chip with the CMOS imaging array, then integration and signal processing are simplified, but light-induced leakage increases degrading image quality
Solution Approach 1:
The image sensor is divided into two separate chips: the top chip contains the CMOS imaging array while the bottom chip contains the light-sensitive circuit elements (memory latches, readout circuits). This segmentation physically separates light-sensitive components from the light path, eliminating light-induced leakage while maintaining functional integration through vertical stacking and bonding interfaces.
Solution Approach 2:
The circuit elements are moved from the planar two-dimensional layout on the top chip to a three-dimensional stacked configuration on the bottom chip. This vertical dimensionality change allows light-sensitive components to be positioned below the photodetector array, naturally shielding them from incident light while maintaining electrical connectivity through vertical interconnects.
2Object-affected harmful factors
If a dedicated photo-shield is added to protect light-sensitive circuit elements, then light-induced leakage is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The light-sensitive circuit elements are extracted from the top chip and relocated to the bottom chip. This extraction eliminates the need for additional photo-shielding structures within the pixel array, as the sensitive components are naturally positioned outside the light path. The shielding function is achieved through the structural arrangement rather than additional protective components.
Solution Approach 2:
The stacked chip structure itself provides the shielding function. The top chip with the CMOS imaging array acts as a natural shield for the bottom chip containing light-sensitive circuit elements. This self-shielding approach eliminates the need for separate photo-shield components, reducing device complexity while maintaining protection against light-induced leakage.
3Measurement precision
If in-pixel memory is incorporated in the top chip, then integration period control is improved, but light-sensitive circuit elements are exposed to light causing leakage
Solution Approach 1:
The memory function is segmented from the photodetector array and relocated to the bottom chip. Each pixel's integration period control is maintained through vertical interconnects between the top chip photodetectors and the bottom chip memory latches. This segmentation allows precise integration control while protecting memory elements from light exposure.
Solution Approach 2:
Vertical interconnect structures serve as intermediaries between the top chip photodetectors and the bottom chip memory elements. These interconnects transmit control signals for integration period management while physically separating the light-sensitive memory circuits from direct light exposure, maintaining functional control without compromising protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces light-induced leakage, enhances image quality by minimizing motion-related artifacts, and increases the flexibility of image signal processing, while maintaining high resolution and low power consumption.
Implementation Method 1
The bottom chip includes light-sensitive circuit elements that need to be shielded from light
Data Source
AI summary
An example imaging sensor system includes a backside-illuminated CMOS imaging array formed in a first semiconductor layer of a first wafer. The CMOS imaging array includes an N number of pixels, where each pixel includes a photodiode region. The first wafer is bonded to a second wafer at a bonding interface between a first metal stack of the first wafer and a second metal stack of the second wafer. A storage device is disposed in a second semiconductor layer of the second wafer. The storage device includes at least N number of storage cells, where each of the N number of storage cells are configured to store a signal representative of image charge accumulated by a respective photodiode region. Each storage cell includes a circuit element that is sensitive to light-induced leakage.