Stacked-Chip Image Sensor Vertical Interconnects for High Frame Rate
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Solution Overview
Problem
Conventional imaging systems with stacked-chip image sensors face limitations in frame rate and signal-to-noise ratio, particularly in capturing images from low-light scenes and scenes with moving objects, due to shared column and row lines, leading to inadequate representation of transient image signals and motion artifacts.
Innovation Solution
The implementation of vertical conductive interconnects, such as through-silicon vias, to couple image pixel sub-arrays directly to control circuitry, allowing simultaneous readout of multiple pixel rows and columns, and the use of stacked processing circuitry to dynamically adjust integration times based on image content, enabling high-frame-rate capture and improved signal-to-noise ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If shared column and row lines are used to connect image sensor pixels to control circuitry, then device complexity is reduced, but frame rate and data readout speed are limited
Solution Approach 1:
The patent transitions from a planar (2D) connection architecture to a three-dimensional stacked architecture. Image sensor pixels are connected to control circuitry through vertical interconnects (via holes) that extend through the substrate, adding a vertical dimension to the connection path. This enables simultaneous readout of multiple pixel rows and columns, dramatically increasing frame rate without being constrained by shared lateral conductors.
Solution Approach 2:
The patent divides the image sensor into multiple pixel arrays that can be independently connected to control circuitry through separate vertical interconnects. Each pixel array can be read out through its own dedicated pathway, eliminating the bottleneck of shared column and row lines and enabling parallel data acquisition from multiple regions of the sensor.
2Reliability
If a predetermined integration time is used for all pixels, then device complexity is reduced, but image quality in varying light conditions deteriorates
Solution Approach 1:
The patent implements dynamic integration time control where the exposure duration for each pixel array can be independently adjusted based on scene requirements. The control circuitry receives image data from multiple pixel arrays captured at different integration times and selectively combines them, allowing the system to adapt to varying light conditions and motion levels in different regions of the scene.
Solution Approach 2:
The patent applies different integration times to different pixel arrays based on local scene characteristics. Regions with motion or varying light conditions can use shorter or longer exposures independently, optimizing image quality for each local area while maintaining a unified sensor structure.
3Reliability
If longer integration time is used to improve signal-to-noise ratio in low light, then image quality improves, but motion artifacts increase
Solution Approach 1:
The patent captures multiple image frames at different time intervals with varying integration times. By periodically sampling the scene at different exposure durations, the system can select or combine frames that best represent the static portions of the scene with high signal-to-noise ratio while excluding or correcting frames that contain motion artifacts.
Solution Approach 2:
The control circuitry analyzes image data from multiple pixel arrays to detect motion and selectively determines which frames to combine. This feedback mechanism allows the system to identify regions with motion and adjust the integration time or frame selection accordingly, preventing motion artifacts from degrading the overall image quality while maintaining high signal-to-noise ratio in static regions.
Data Source
AI summary
Imaging systems may be provided with stacked-chip image sensors. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels and processing circuitry. The image pixel array may be coupled to the processing circuitry through an array of vertical metal interconnects. The image pixel array may be partitioned into image pixel sub-arrays configured to capture image data using one or more integration times. The processing circuitry may determine motion information for the image data captured by each pixel sub-array and may determine integration times for each pixel sub-array. The pixel sub-arrays may capture additional image data using the determined integration times. The additional image data may be combined to generate final image frames having short integration pixel values and long integration pixel values. The processing circuitry may output the final image frames to off-chip image processing circuitry.