Stacked-Chip Image Sensor Vertical Interconnects Readout Rate

Solution Overview

Problem

Conventional imaging systems with shared column and row lines for image sensor pixels limit the rate of image data readout and control signal supply, restricting the capture and output of image frames.

Innovation Solution

The implementation of stacked-chip image sensors with vertical conductive interconnects, such as through-silicon vias, allows for simultaneous communication between image pixel sub-arrays and control circuitry, enhancing data readout and control signal distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If shared column and row lines are used to connect image sensor pixels to control circuitry, then device complexity is reduced, but data readout rate and control signal supply rate are limited

Engineering Contradiction:

Improvedata readout rateVSAvoidinterconnect structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent transitions from a planar two-dimensional interconnect structure to a three-dimensional stacked architecture. Image sensor pixels are arranged on a first substrate while control circuitry is placed on a second substrate, with vertical conductive vias providing direct through-substrate connections. This dimensional change eliminates the need for shared row and column scanning lines, enabling simultaneous independent access to all pixels and dramatically increasing data readout rate.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the image sensor system into separate functional layers on different substrates. The first substrate contains only image sensor pixels, while the second substrate contains control circuitry and memory. This segmentation allows each layer to be optimized independently and enables parallel processing operations, improving overall productivity without excessive complexity.

Inventive Principle:

Principle #1Segmentation

2Productivity

If stacked-chip architecture with vertical conductive interconnects is used, then data readout bandwidth is increased, but manufacturing complexity increases

Engineering Contradiction:

Improveimage capture rateVSAvoidstacked-chip fabrication

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

The patent divides the image sensor system into separate functional layers on different substrates. The first substrate contains only image sensor pixels, while the second substrate contains control circuitry and memory. This segmentation allows each layer to be optimized independently and enables parallel processing operations, improving overall productivity without excessive complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary bonding layer between the first and second substrates that facilitates alignment and electrical connections. This intermediary structure simplifies the bonding process by providing reference marks and conductive pathways, reducing manufacturing difficulty despite the increased complexity of the stacked architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Loss of time

If multiple pixel rows and columns are read out simultaneously, then processing latency is reduced, but interconnect complexity increases

Engineering Contradiction:

Improveprocessing latencyVSAvoidvertical interconnect structure

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent transitions from a planar two-dimensional interconnect structure to a three-dimensional stacked architecture. Image sensor pixels are arranged on a first substrate while control circuitry is placed on a second substrate, with vertical conductive vias providing direct through-substrate connections. This dimensional change eliminates the need for shared row and column scanning lines, enabling simultaneous independent access to all pixels and dramatically increasing data readout rate.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent extracts the control circuitry from the pixel array substrate and places it on a separate second substrate. This extraction eliminates the bottleneck of shared scan lines within the pixel plane, allowing each pixel to be independently and simultaneously accessed through its dedicated vertical via connection, thereby reducing processing latency.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS9350928B2Image data compression using stacked-chip image sensors

Publication Date: 2016.05.24 SEMICON COMPONENTS IND LLC

AI summary

Imaging systems may be provided with stacked-chip image sensors. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels and processing circuitry. The image pixel array may be coupled to the processing circuitry through an array of vertical metal interconnects. The image pixel array may be partitioned into image pixel sub-arrays configured to capture image data at a capture frame rate. The processing circuitry may compress image data associated with each image pixel sub-array in parallel and may output the compressed image data to off-chip image processing circuitry at an output frame rate that is less than the capture frame rate. The processing circuitry may determine respective compression block sizes for each image pixel sub-array with which to compress the associated image data and may determine respective output frame rates for image data from each image pixel sub-array.