Stacked On-Chip Inductor Layout for High Q in Compact Area

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Solution Overview

Problem

Conventional on-chip inductors with multiple metal layers as spiral-type coils suffer from reduced quality factor (Q value) and increased planar size due to less thickness, leading to higher manufacturing costs for achieving desired inductance.

Innovation Solution

A multilayer-type on-chip inductor structure is designed with inter-metal dielectric (IMD) layers featuring a combination of spiral-type and open ring-type coils, where the second metal winding portion vertically overlaps the first, and via-structure regions are used for electrical connections, allowing for increased coil length and reduced occupied area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple metal layers are used as spiral-type coils, then the inductance can be increased, but the quality factor (Q value) is reduced due to less thickness

Engineering Contradiction:
ImproveinductanceVSAvoidquality factor
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from a planar spiral configuration to a three-dimensional stacked configuration with multiple metal layers. The first and second metal winding portions are disposed in different dielectric layers and vertically overlap each other, utilizing the vertical dimension to increase effective coil length and inductance while maintaining thin profile and reducing conductor loss through optimized current distribution across layers.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested coil structures where open ring-type coils and spiral-type coils are combined within the same metal layer. The first open ring-type coil surrounds the first spiral-type coil, and the second open ring-type coil surrounds the second spiral-type coil, creating concentric nested patterns that maximize space utilization and inductance density.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Quantity of substance

If the planar size of the inductor is increased to achieve desired inductance, then the inductance can be increased, but the manufacturing cost increases

Engineering Contradiction:
ImproveinductanceVSAvoidmanufacturing cost
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent utilizes the vertical dimension by stacking metal winding portions in multiple dielectric layers. This allows the inductor to achieve the desired inductance value within a compact planar footprint by extending the coil structure into the third dimension, thereby avoiding the need to increase chip area and associated manufacturing costs.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent integrates the inductor structure with existing interconnect and redistribution layers of the semiconductor device. The metal winding portions are formed using the same metal layers and processes as the device interconnect, eliminating the need for additional dedicated inductor fabrication processes and reducing overall manufacturing complexity and cost.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Area of stationary object

If the planar size of the inductor is reduced, then the occupied area is reduced, but the coil length must be decreased which reduces inductance

Engineering Contradiction:
Improveoccupied areaVSAvoidinductance
Core Design Contradiction:
Area of stationary objectVSQuantity of substance

Solution Approach 1:

The patent resolves this contradiction by transitioning from a two-dimensional planar coil to a three-dimensional stacked coil structure. The first and second metal winding portions are disposed in different dielectric layers and vertically overlap, allowing the coil length to be extended in the vertical dimension while maintaining a compact planar footprint. This enables high inductance values within small occupied areas.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs nested coil configurations where multiple coils are arranged concentrically within the same planar space. The open ring-type coils surround the spiral-type coils, and adjacent metal layers are vertically aligned to create nested three-dimensional structures that maximize the effective coil length within the available planar area.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS20240266283A1Multilayer-type on-chip inductor structure
Publication Date: 2024.08.08 VIA LABS INC
  • US20240266283A1 patent drawing
  • US20240266283A1 patent drawing
  • US20240266283A1 patent drawing

AI summary

A multilayer-type on-chip inductor structure includes an inter-metal dielectric (IMD) layer having an inductor central region, a first metal winding portion disposed in the IMD layer, and a second metal winding portion disposed in the IMD layer and electrically connected to the overlying first metal winding portion. The first metal winding portion includes a first spiral-type coil surrounding the inductor central region and a first open ring-type coil surrounding the first spiral-type coil. The second metal winding portion includes a second spiral-type coil vertically overlapping the first spiral-type coil and the first open ring-type coil, so that the outermost-turn coil of the second spiral-type coil corresponds to the first open ring-type coil.