Stacked Semiconductor Chip Inductor Magnetic Field Shielding
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Solution Overview
Problem
In stacked semiconductor chips, the inductance of inductors decreases due to counter-electromotive forces caused by magnetic fields, leading to reduced signal quality and resonance frequency variations, making it challenging to maintain inductance without increasing component count and cost.
Innovation Solution
The solution involves stacking semiconductor chips with a first inductor in one chip and an arrangement-restricted region in the second chip, where a dummy pattern or a second inductor with spiral wiring is placed to counteract the magnetic field, thereby inhibiting inductance decrease and electromagnetic noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If circuits are dispersed to multiple stacked semiconductor chips to reduce mounting area, then mounting area is reduced, but inductance of the inductor decreases due to counter-electromotive force from magnetic fields
Solution Approach 1:
An electromagnetic shield is introduced as an intermediary component between the inductor in the first semiconductor chip and the circuit in the second semiconductor chip. This shield blocks the magnetic field from the upper circuit, preventing it from generating counter-electromotive force in the inductor, thereby maintaining inductance while allowing chip stacking for area reduction
Solution Approach 2:
The harmful magnetic field effect is extracted and isolated by placing the electromagnetic shield specifically in the region corresponding to the inductor. This separates the inductor from the interfering magnetic field environment, allowing the inductor to maintain its electrical characteristics despite the presence of stacked chips
2Reliability
If an electromagnetic shield is added above the inductor to inhibit inductance decrease, then inductance is maintained, but the number of components increases, thereby increasing cost
Solution Approach 1:
The electromagnetic shield is merged with the existing semiconductor chip structure, specifically formed on the surface of the first semiconductor chip in the region corresponding to the inductor. This integration approach incorporates the shield function into the chip fabrication process without requiring separate component assembly, thereby maintaining inductance while avoiding additional component costs
Solution Approach 2:
The first semiconductor chip serves multiple functions: it contains the inductor circuit and simultaneously provides the electromagnetic shield function through its surface structure. This multi-functionality eliminates the need for a separate dedicated shield component, reducing overall device complexity while maintaining inductance protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively maintains inductance and reduces electromagnetic noise, enhancing signal quality without increasing component count or cost, thus addressing the challenge of inductance reduction in stacked semiconductor chips.
Implementation Method 1
the magnetic field generated in the upper circuit to occur in the inductor
Implementation Method 2
a counter-electromotive force due to the magnetic field generated in the upper circuit to occur in the inductor
Implementation Method 3
The first and second inductors may generate individual magnetic fields in an identical direction
Data Source
AI summary
To inhibit a decrease in inductance of an inductor in a plurality of semiconductor chips that are stacked. A semiconductor device includes: first and second semiconductor chips that are stacked; a first inductor; an arrangement-restricted region; and a circuit. In the semiconductor device, the first inductor is arranged in the first semiconductor chip. The arrangement-restricted region is provided in a region of the second semiconductor chip corresponding to the first inductor. The circuit is arranged in a region of the second semiconductor chip not corresponding to the arrangement-restricted region.