Stacked Chip Package With Insulated Inner Leads
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Solution Overview
Problem
Conventional chip-stacked package structures face challenges such as increased thickness or limited chip stacking due to spacer usage, and reliability and yield issues during wire-bonding processes, particularly with high-pressure mold-flow injection causing wire shifting and shorting.
Innovation Solution
An offset chip-stacked package structure with a leadframe featuring inner leads coated with an insulating layer and selectively formed metal pads, allowing for flexible circuit design and improved reliability through enhanced electrical connections and reduced wire crossing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spacers are used to prevent chip contact during wire-bonding, then wire crossing is prevented, but package thickness increases
Solution Approach 1:
The patent removes the spacer component entirely from the package structure. Instead of using a physical spacer to prevent wire crossing, the invention uses a leadframe with inner leads that are positioned to provide natural wire routing paths, eliminating the need for thickness-increasing spacers while maintaining wire bonding reliability
Solution Approach 2:
The inner leads of the leadframe serve as intermediary elements that guide and separate wires during bonding. These inner leads are strategically positioned to act as physical barriers and routing guides, preventing wire crossing without requiring additional spacer components, thus solving the contradiction between reliability and thickness
2Productivity
If chips are stacked with similar sizes, then stacking density is improved, but wire jumping and crossing occur during bonding
Solution Approach 1:
The inner leads act as intermediary structures that facilitate wire routing between similarly-sized stacked chips. By providing designated wire paths along the inner leads, the invention enables high-density stacking of similar-sized chips while preventing wire jumping and crossing through structured wire guidance
Solution Approach 2:
The invention introduces vertical dimension utilization through stacked chips with inner leads extending at different heights. This multi-level lead structure creates three-dimensional wire routing paths, allowing wires to connect between similarly-sized chips without crossing by utilizing vertical separation and offset positioning
3Ease of manufacture
If high-pressure mold-flow injection is applied during molding, then encapsulation is completed, but wires shift and shorting occurs
Solution Approach 1:
The patent provides beforehand cushioning by creating a robust wire bonding structure before molding. The inner leads are positioned and wires are bonded with sufficient mechanical strength and positional stability to withstand the subsequent high-pressure mold-flow injection process, preventing wire shifting and shorting while maintaining manufacturing efficiency
Data Source
AI summary
The present invention provides a stacked chip package structure with leadframe having inner leads with transfer pad, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and vertically distant from the plurality of inner leads; an offset chip-stacked structure formed with a plurality of chips stacked together, the offest chip-stacked structure being set on the die pad and electrically connected to the plurality of inner leads arranged in rows facing each other; and an encapsulant covering the offset chip-stacked structure and the leadframe, the plurality of outer leads extending out of said encapsulant; the improvement of which being that the inner leads of the leadframe are coated with an insulating layer and a plurality of metal pads are selectively formed on the insulating layer.