Stacked Chip Interface Layout for Smaller Package Footprint
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Solution Overview
Problem
The challenge of reducing the plane dimension of chips in electronic devices is exacerbated by the need for multiple interface circuits due to homogeneous redistribution layer designs, leading to redundancy and increased chip size.
Innovation Solution
Implementing a heterogeneous design for redistribution layers on stacked chips, where each die has only one active interface circuit, reducing redundancy and plane dimension by insulating and independently connecting interface circuits through distinct masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If homogeneous redistribution layer design is used with multiple interface circuits, then signal transmission capability is improved, but chip plane dimension increases
Solution Approach 1:
The chip is divided into multiple dies (first die, second die, third die) stacked vertically, with each die having its own independent interface circuit and redistribution layer. This segmentation allows signal transmission capability to be distributed across multiple independent circuits rather than requiring all interfaces on a single large chip plane.
Solution Approach 2:
The patent transitions from a two-dimensional homogeneous layout to a three-dimensional stacked architecture. Interface circuits are distributed across multiple vertical layers (dies) instead of being confined to a single plane, effectively using the vertical dimension to accommodate multiple interfaces without increasing chip plane dimension.
2Adaptability or versatility
If multiple interface circuits are integrated on a single die, then signal transmission capability is improved, but device complexity increases
Solution Approach 1:
The interface circuit functionality is segmented across multiple dies rather than concentrated on one die. Each die has its own simplified interface circuit and redistribution layer, avoiding the complexity of integrating multiple interface circuits on a single die and the associated complex mask patterns.
Solution Approach 2:
Each die is designed with local quality - having its own dedicated interface circuit and redistribution layer optimized for that specific die's requirements. This local optimization simplifies the design and mask patterns for each individual die compared to a global homogeneous design.
3Area of moving object
If heterogeneous redistribution layer design is implemented, then chip plane dimension is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses vertical stacking of multiple dies to reduce the horizontal plane dimension. Each die in the stack has its own heterogeneous redistribution layer design, allowing compact 2D layout while distributing interface circuits across the 3D vertical space. The insulation requirement is managed through vertical separation between dies rather than horizontal separation on a single chip.
Data Source
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Figure 3~4A
Figure 4B~5A
AI summary
Embodiments of this application provide a chip stacking structure and an electronic device, and relate to the field of chip manufacturing technologies, to alleviate a problem of a large plane dimension of a chip. In the chip stacking structure, a third die, a second die, and a first die are sequentially stacked on a carrier board. A first redistribution layer and a first interface component of the first die form a first interface circuit, and a second redistribution layer and a second interface component of the second die form a second interface circuit. A first conductive structure penetrates through at least the second die and the third die, and a second conductive structure penetrates through at least the third die. The first interface circuit of the first die and the second interface circuit of the second die are separately electrically connected to another component through the insulated first conductive structure and the insulated second conductive structure.