Stacked Semiconductor Chip Fabrication via Isolation Layer Planarization
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Solution Overview
Problem
The challenge in semiconductor device fabrication lies in achieving improved thickness uniformity and edge profile to enhance yield, quality, and performance, particularly as devices are scaled down, where existing methods face issues with gap filling and substrate processing.
Innovation Solution
A method involving bonding multiple stacking chips onto a bottom substrate, forming isolation and capping layers, and performing thinning and planarization processes to expose through substrate vias and achieve a flat surface, which includes using hybrid bonding, dry etch processes, and specific material selections like oxide, nitride, and oxynitride layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used for scaling down semiconductor devices, then device density increases, but thickness uniformity and edge profile deteriorate
Solution Approach 1:
The fabrication process is divided into distinct stages: forming isolation layers in gaps between stacking chips, performing thinning processes, and conducting planarization. This segmentation allows each process step to be optimized independently, improving thickness uniformity while managing the complexity of device scaling.
Solution Approach 2:
Isolation layers are formed in the gaps between stacking chips before the thinning process. This preliminary action prepares the structure for subsequent thinning and planarization, ensuring that thickness uniformity and edge profile are maintained throughout the fabrication sequence.
2Manufacturing precision
If gap filling is performed without proper isolation layer formation, then manufacturing complexity reduces, but thickness uniformity and edge profile worsen
Solution Approach 1:
Isolation layers are selectively formed only in the gap regions between stacking chips, providing localized quality enhancement. This approach improves edge profile and thickness uniformity in critical areas without unnecessarily complicating the entire fabrication process.
Solution Approach 2:
The isolation layer acts as an intermediary material that fills the gaps between stacking chips. This mediator enables proper thickness control and edge profile formation during subsequent thinning and planarization processes, resolving the contradiction between precision and complexity.
3Loss of energy
If carrier substrates are used in the fabrication process, then manufacturing simplicity increases, but thermal dissipation and cost worsen
Solution Approach 1:
The method eliminates the carrier substrate from the fabrication process entirely. By bonding stacking chips directly to the bottom substrate and forming isolation layers in the gaps, the process removes the thermal and cost disadvantages associated with carrier substrates while maintaining manufacturing feasibility.
Solution Approach 2:
The bottom substrate and isolation layers work together to provide the necessary support and thermal management functions that would otherwise require a carrier substrate. This self-service approach improves thermal dissipation and reduces costs without significantly increasing fabrication complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves thickness uniformity and edge profile, leading to enhanced yield, quality, and performance of semiconductor devices by eliminating the need for carrier substrates and optimizing thermal dissipation and manufacturing costs.
Implementation Method 1
bonding a first stacking chip and a second stacking chip onto the bottom substrate
Implementation Method 2
a process pressure of the hybrid bonding process is between about 100 MPa and about 150 MPa
Implementation Method 3
the removal process is a dry etch process
Implementation Method 4
an etch rate ratio of the first isolation layer to a substrate of the first stacking chip is between about 15:1 and about 2:1 of the dry etch process
Implementation Method 5
the method for fabricating the semiconductor device includes a thermal annealing process after bonding the first stacking chip and the second stacking chip onto the bottom substrate
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The method includes providing a bottom substrate; bonding a first stacking chip and a second stacking chip onto the bottom substrate; conformally forming a first isolation layer to cover the first and second stacking chips and to at least partially fill a gap between the first and second stacking chips; performing a thinning process to expose back surfaces of the first and second stacking chips; performing a removal process to expose through substrate vias of the first and second stacking chips; forming a first capping layer to cover the through substrate vias of the first and second stacking chips; and performing a planarization process to expose the through substrate vias of the first and second stacking chips and provide a substantially flat surface.