Stacked Chip Junction Layout for Reliable Pixel Signal Transmission
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Solution Overview
Problem
Existing semiconducting devices with stacked chips face connection failures in the path for transmitting pixel signals, leading to incomplete signal transmission between chips.
Innovation Solution
The semiconducting device employs a configuration with multiple conductive patterns, primarily made of copper, connected via junction portions and insulation layers, ensuring reliable electrical connections between chips in the signal transmission path, with varying numbers of junction portions and contacts to optimize reliability and characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple copper conductive patterns are joined via junction portions to transmit pixel signals between chips, then signal transmission reliability is improved, but connection failures may still occur leading to incomplete signal transmission
Solution Approach 1:
The patent applies beforehand cushioning by providing multiple redundant conductive patterns (first and second conductive patterns on each chip) with multiple junction portions between chips. This redundancy ensures that if one connection path fails, alternative paths remain available to maintain signal transmission, thus cushioning against connection failures before they compromise overall system reliability.
2Reliability
If conductive patterns are joined on a junction plane between stacked chips, then electrical connection between chips is established, but insulation between adjacent conductive patterns must be ensured
Solution Approach 1:
The patent applies local quality by placing insulation layers specifically at the spaces between adjacent conductive patterns (first and second conductive patterns) on the junction plane. This localized insulation approach ensures electrical isolation where needed while maintaining conductive connections where required, resolving the contradiction between establishing reliable electrical connections and ensuring proper insulation.
3Reliability
If multiple junction portions are used to connect conductive patterns between chips, then connection redundancy is improved, but device complexity increases
Solution Approach 1:
The patent applies merging by integrating multiple junction portions into a unified junction plane structure where first and second conductive patterns from different chips are simultaneously connected. This combines multiple connection functions into a single integrated structure, providing connection redundancy while minimizing the increase in device complexity compared to separate multi-layer connection structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration provides adequate and reliable connections between chips, ensuring effective transmission of pixel signals by optimizing the number of junction portions and contacts, thereby enhancing the reliability and characteristics of the signal transmission path.
Implementation Method 1
the first conductive pattern and the third conductive pattern are joined to each other on a junction plane
Implementation Method 2
an insulation layer is arranged at least in one of spaces between the first conductive pattern and the second conductive pattern, and between the third conductive pattern and the fourth conductive pattern
Data Source
AI summary
A first conductive pattern and a third conductive pattern are joined to each other in a junction plane, and a second conductive pattern and a fourth conductive pattern are joined to each other in the junction plane, and an insulation layer is arranged at least in one of spaces between the first conductive pattern and the second conductive pattern and between the third conductive pattern and the fourth conductive pattern.