Stacked Chip Layout for Decoupling Capacitance and Low-Latency Memory
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Solution Overview
Problem
On-chip heterogeneous processors face issues such as insufficient capacitance density of decoupling capacitors, high equivalent series inductance values, low memory capacity, and increased latency in data storage and reading, particularly in complex mobile applications.
Innovation Solution
A chip design comprising a first chip component with processor units and a second chip component with integrated passive devices and memories, arranged in stack, where integrated passive devices are connected to processor units to enhance capacitance density and reduce equivalent series inductance, and memories provide high-capacity, low-latency data storage and reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If on-chip heterogeneous processors are used to satisfy complex mobile application requirements, then processing capability is improved, but capacitance density of decoupling capacitor becomes insufficient
Solution Approach 1:
The patent combines multiple chip components (processor units, integrated passive devices, and memories) into a single stacked chip structure. The integrated passive devices are positioned between the processor units and substrates, merging decoupling capacitor functions directly into the chip architecture rather than using separate external components, thereby improving capacitance density while maintaining processing capability.
2Productivity
If on-chip heterogeneous processors are used, then processing capability is improved, but equivalent series inductance value increases
Solution Approach 1:
The integrated passive devices serve as intermediary elements positioned between the processor units and the substrates. These passive devices include decoupling capacitors that act as mediators to filter noise and reduce equivalent series inductance effects, thereby protecting the high-performance processor units from inductance-related harmful factors while maintaining processing capability.
3Quantity of substance
If memory capacity is increased, then data storage capability is improved, but latency in data storage and reading increases
Solution Approach 1:
The patent transitions from traditional planar chip architecture to a three-dimensional stacked architecture. Memories are positioned in different layers and stacked vertically, allowing parallel data access paths and reducing the physical distance data must travel. This dimensional change enables increased memory capacity while maintaining low latency through parallelism and reduced signal path lengths.
4Adaptability or versatility
If multiple chip components are integrated, then functionality is improved, but device complexity increases
Solution Approach 1:
The patent segments the chip into distinct functional layers: processor units in one layer, integrated passive devices in another layer, and memories in additional layers. This segmentation allows each layer to be optimized independently for its specific function while the overall stack provides integrated functionality. The modular segmented structure manages complexity by organizing diverse components into manageable functional blocks.
Data Source
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AI summary
A chip includes a first chip component and a second chip component. The first chip component includes one or more processor units. The second chip component includes one or more integrated passive devices and one or more memories. At least one of the integrated passive devices is connected to at least one of the processor units, and at least one of the memories is connected to at least one of the processor units. According to the chip of the present invention, the integrated passive device of the second chip component is connected to the processor unit of the first chip component, thereby utilizing the high capacitance density of the integrated passive component to provide the sufficient capacitance density of decoupling capacitor and the lower equivalent series inductance value for the processor unit; and the memory of second chip component is connected to the processor unit of the first chip component, so that the memory can provide high-capacity, low latency data reading and storage for the processor unit.