Stacked Chip Packaging With Integrated Metal Shielding Layer
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Solution Overview
Problem
Conventional semiconductor packaging methods for high-frequency chips face challenges with electromagnetic interference (EMI) and heat-dissipation efficiency due to strong electromagnetic waves, and they are costly and heavy, making them unsuitable for mass production with low weight and low cost requirements.
Innovation Solution
A packaging method using a substrate with a dielectric layer and a metal layer, where chips are stacked between the dielectric and metal layers, or between two surfaces of the metal layer, with a conducting trace area and a shielding area, and a solder mask is formed to connect the chips electrically and provide a high heat-dissipating and shielding effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a metal mask is used to cover the package and connect to ground to solve EMI problem, then electromagnetic interference is reduced, but weight and cost increase and mass production becomes difficult
Solution Approach 1:
The patent extracts the shielding function from a separate metal mask component and integrates it into the substrate structure itself through a metal layer formed directly on the substrate. This eliminates the need for an additional metal mask component, reducing overall weight and simplifying the packaging structure while maintaining EMI shielding effectiveness.
Solution Approach 2:
The patent merges the substrate and shielding layer into a single integrated structure, where the metal layer is formed directly on the substrate surface. This combination eliminates the need for separate shielding components and their associated mounting processes, reducing weight, cost, and complexity while improving mass production capability.
2Object-affected harmful factors
If a metal mask is used to cover the package and connect to ground to solve EMI problem, then electromagnetic interference is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The shielding metal layer is formed on the substrate during the substrate manufacturing process itself, before the packaging assembly is completed. This preliminary integration of the shielding function into the substrate fabrication process eliminates subsequent shielding component installation steps, simplifying manufacturing and enabling mass production.
Solution Approach 2:
The patent merges the substrate and shielding layer into a single integrated structure, where the metal layer is formed directly on the substrate surface. This combination eliminates the need for separate shielding components and their associated mounting processes, reducing weight, cost, and complexity while improving mass production capability.
3Temperature
If chips are stacked between dielectric layer and metal layer, then heat dissipation and shielding effects are improved, but manufacturing process becomes more complex
Solution Approach 1:
The metal layer serves multiple functions simultaneously: it provides electromagnetic shielding, acts as a heat dissipation path, and serves as an electrical connection layer. This multi-functionality eliminates the need for separate shielding and thermal management components, simplifying the overall packaging structure and process despite the stacked chip configuration.
Solution Approach 2:
The patent uses a composite structure with a dielectric layer and metal layer formed on the substrate, creating a multi-functional packaging structure that integrates shielding, thermal management, and electrical connection functions. This composite approach simplifies the overall system despite the complex stacked chip arrangement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method achieves a high heat-dissipating and shielding effect while simplifying the packaging process and reducing costs, addressing the EMI issues and enabling mass production of lightweight, cost-effective semiconductor packages.
Implementation Method 1
a metal layer, where the metal layer includes a conducting trace area and a shielding area
Implementation Method 2
achieves a high heat-dissipating effect and a metal shield effect for the chip
Data Source
AI summary
A package structure with a plurality of chips stacked on each other includes a substrate, a first chip and second chip. The substrate has a dielectric layer, a metal layer having a conducting trace area and a shielding area formed on the dielectric layer, and a solder mask formed on the conducting trace area. The first chip and the second chip are electrically connected to the conducting trace area and arranged on the solder mask respectively. The first chip has a package body connected with one surface of the metal layer for arranging the first chip between the solder mask and the shielding area of the metal layer. The second chip has a package body connected with the other surface of the metal layer for arranging the second chip between the solder mask and the shielding area of the metal layer.