Stacked Semiconductor Chip Micro-Bump Pad Routing
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Solution Overview
Problem
In three-dimensional LSI semiconductor devices, micro-bump pads on the surface of stacked chips can be exposed and disconnected, leading to a risk of static electricity-induced breakdown, and connecting pull-up or pull-down resistances to these pads increases parasitic capacitance, which is undesirable for high-frequency signal propagation.
Innovation Solution
The semiconductor device design includes a configuration where micro-bump pads connected to TSVs are either connected to each other or to the output terminals of the chips, avoiding external connection and thus eliminating the need for pull-up or pull-down resistances, thereby reducing parasitic capacitance and preventing static electricity breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If micro-bump pads are left open and externally exposed, then device complexity is reduced, but reliability deteriorates due to risk of static electricity-induced breakdown
Solution Approach 1:
The harmful function of the micro-bump pad (external connection) is extracted and removed. The pad structure is reconfigured so that the pad electrode does not extend to the external surface, eliminating the exposure to static electricity while maintaining the electrical connection function through internal routing via TSVs and wiring layers
Solution Approach 2:
Instead of having the pad electrode connect externally to input terminals, the connection is inverted to route through internal TSVs and wiring layers to output terminals. This reverses the traditional pad configuration, making the pad non-exposed while maintaining functionality
2Reliability
If pull-up resistance or pull-down resistance is connected to micro-bump pads, then reliability improves by preventing static electricity breakdown, but parasitic capacitance increases, worsening high-frequency signal propagation
Solution Approach 1:
The need for pull-up or pull-down resistances is eliminated by extracting the harmful exposure condition. By making the pad non-exposed through internal routing, the pad naturally avoids static electricity damage without requiring additional protective components, thus avoiding the parasitic capacitance problem
Solution Approach 2:
Internal wiring layers and TSVs serve as intermediaries to route the pad connection away from external exposure. This intermediary routing structure protects the pad from static electricity without introducing resistive components that would add parasitic capacitance
3Speed
If micro-bump pads are connected to TSVs for direct chip-to-chip connection, then signal propagation speed improves, but parasitic capacitance increases when pull-up or pull-down resistances are added
Solution Approach 1:
The source of parasitic capacitance (pull-up or pull-down resistances) is eliminated by removing the need for these components. The pad is reconfigured to be non-exposed with internal routing, which naturally prevents static electricity damage without adding resistive elements that would increase parasitic capacitance
Data Source
AI summary
A semiconductor device, includes: a first semiconductor chip including: a first substrate; a first via; a first rear surface-side pad connected to the first via; a first wiring layer; a first front surface-side pad formed on the first wiring layer; and an input circuit formed in the first substrate, an input signal wire connecting the first via, the first front surface-side pad, and an input terminal of the input circuit; and a second semiconductor chip including: a second substrate; a second wiring layer; a second front surface-side pad; and an output circuit formed in the second substrate, an output signal wire connecting the second front surface-side pad to an output terminal of the output circuit. The second semiconductor chip is stacked on a rear surface side of the first semiconductor chip, and the first rear surface-side pad and the second front surface-side pad are connected.