Stacked Semiconductor Chip Noise Reduction via Shifted Pad Alignment
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Solution Overview
Problem
Conventional Multi Chip Packages (MCPs) face challenges in reducing noise superimposed on bonding wires due to increased wire length, which affects the operation speed and data transfer bandwidth, as there is no existing proposal for wire bonding that addresses this issue effectively.
Innovation Solution
The semiconductor device features a configuration where semiconductor chips are stacked with conductive pads aligned orthogonally and shifted at predetermined intervals, with bonding wires extending linearly in a direction orthogonal to the chip alignment, ensuring non-overlapping pads and reduced wire length for signal communication, thereby minimizing noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires are lengthened to connect conductive pads on stacked semiconductor chips, then electrical connection is achieved, but noise superimposed on the wires increases
Solution Approach 1:
The patent shifts the problem from a vertical connection approach to a horizontal arrangement by aligning conductive pads in the planar direction. Multiple conductive pads are arranged side-by-side on each chip, and bonding wires connect corresponding pads across adjacent chips horizontally, converting a three-dimensional vertical stacking problem into a two-dimensional planar connection problem, thereby reducing wire length and noise.
Solution Approach 2:
The patent divides the signal transmission path into multiple parallel bonding wires, each connecting corresponding conductive pads between adjacent chips. By segmenting the connection into multiple short wire segments rather than one long vertical wire, the total noise is reduced while maintaining electrical connectivity.
2Productivity
If multiple NAND type flash memories are divided for multiple channels to increase data transfer bandwidth, then operation speed is improved, but the number of bonding wires increases leading to increased noise
Solution Approach 1:
The patent arranges conductive pads in the planar direction rather than vertically, allowing multiple bonding wires for different channels to be laid out side-by-side in the horizontal plane. This dimensional reorganization enables parallel signal transmission for multiple channels while keeping each wire short, thus increasing bandwidth without proportionally increasing noise.
3Ease of manufacture
If conventional wire bonding methods are used for stacked semiconductor chips, then manufacturing is simplified, but bonding wire length cannot be reduced leading to increased noise
Solution Approach 1:
The patent pre-arranges multiple conductive pads in specific positions on each semiconductor chip before stacking. This preliminary planar arrangement of pads enables subsequent horizontal bonding wire connections to be shorter, reducing noise while maintaining manufacturing simplicity through standardized pad layouts and stacking procedures.
Data Source
AI summary
A semiconductor device comprising a plurality of semiconductor chips and a plurality of electric wirings. The plurality of semiconductor chips are stacked in a first direction, each semiconductor chip of the plurality of semiconductor chips including a plurality of conductive pads that are aligned in an aligning direction, orthogonal to the first direction. The plurality of semiconductor chips are stacked such that each semiconductor chip is shifted from an adjacent semiconductor chip of the plurality of semiconductor chips by a first predetermined interval in the aligning direction and shifted from the adjacent semiconductor chip by a second predetermined interval in a second direction orthogonal to both the first direction and the aligning direction. The plurality of electric wirings electrically connect the plurality of conductive pads of every other semiconductor chip of the plurality of semiconductor chips, respectively.