3D Stacked Chip Package for Higher Computing in Less Area
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Solution Overview
Problem
The increased computational speed of chips leads to higher development and production costs, necessitating a solution that reduces chip area and production costs while maintaining or enhancing computing performance.
Innovation Solution
A multi-layer stacked chip package design comprising at least two substrates, circuit layers, chips, and insulation layers, where upper and lower layer chip packages are stacked, with blind and insertion holes allowing electrical connections between chips, minimizing production area and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If chip computational speed is increased, then computing performance is improved, but development and production cost increases
Solution Approach 1:
The chip system is segmented into multiple independent chips stacked vertically, with each chip containing specific circuit layers and functional units. This segmentation allows each chip to be manufactured separately at lower cost while achieving high computing performance through parallel operation of multiple chips.
Solution Approach 2:
The patent transitions from a planar chip layout to a three-dimensional stacked architecture. By adding the vertical dimension with multiple chip layers connected through substrates and conductive structures, the system achieves higher computing performance without proportionally increasing the area of individual chips, thereby reducing manufacturing cost.
2Power
If chip computational speed is increased, then computing performance is improved, but chip area increases
Solution Approach 1:
The patent employs a three-dimensional stacked chip architecture where multiple chip layers are vertically arranged and connected through substrates. This vertical stacking enables high computing performance to be achieved within a compact footprint, significantly reducing the area occupied by individual chips compared to traditional planar designs.
Solution Approach 2:
The patent implements a nested structure where circuit layers, chips, and substrates are arranged in concentric or layered configurations. The circuit layers are embedded within substrates, and multiple chip packages are nested vertically, maximizing space utilization and minimizing the overall chip area while maintaining high computing performance.
3Area of stationary object
If multi-layer stacked structure is implemented, then area is reduced, but manufacturing complexity increases
Solution Approach 1:
The complex multi-layer stacked structure is divided into modular units, with each chip package containing specific circuit layers and functional components. This modular segmentation simplifies the manufacturing process by allowing each module to be fabricated and tested independently before final assembly, thereby reducing overall manufacturing complexity despite the three-dimensional architecture.
4Area of stationary object
If multiple chips are stacked, then area is reduced, but electrical connection complexity increases
Solution Approach 1:
The patent introduces substrates as intermediary components between stacked chips. These substrates provide standardized interfaces and conductive pathways that simplify electrical connections between multiple chip layers. The substrates act as mediators that manage the complexity of inter-chip wiring, enabling efficient electrical connectivity without directly connecting every chip to every other chip.
Data Source
AI summary
A multi-layer stacked chip package is provided. A first substrate, a first circuit layer, a first chip, and a first insulation layer form a lower layer chip package while a second substrate, a second circuit layer, a second chip, and a second insulation layer form an upper layer chip package. The upper layer chip package is stacked over the lower layer chip package so that the multi-layer stacked chip package is formed by such stacking mode. One of the at least two chips is used to operate the rest chips or computing functions of the respective chips are combined to increase overall computing performance.