Stacked Semiconductor Chip Layout for Lower Package Height
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Solution Overview
Problem
Current semiconductor devices with laminated semiconductor chips face challenges in reducing the total height of the chip laminated body, leading to increased thickness of the sealing resin and potential electric short circuits due to the absence of lamination regions, which affects heat dissipation and adhesion strength.
Innovation Solution
The semiconductor device incorporates a configuration with die attach films and PI films arranged in specific regions to create lamination areas of varying thickness, allowing for reduced overall height and improved adhesion, while the PI films around chip electrodes enhance protection against external forces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the total height of the chip laminated body is reduced, then the thickness of the sealing resin increases, but this leads to electric short circuits and poor heat dissipation
Solution Approach 1:
The chip laminated body is divided into multiple chips (first chip, second chip, third chip) stacked vertically at different positions. This segmentation allows the total height to be reduced while maintaining proper spacing between chips, preventing electric short circuits even when the overall height is minimized.
Solution Approach 2:
Instead of reducing height uniformly, the invention utilizes vertical stacking in the Z-direction by positioning chips at different heights. This dimensional approach allows compact integration while maintaining adequate sealing resin thickness to prevent short circuits and ensure proper heat dissipation pathways.
2Length of stationary object
If the total height of the chip laminated body is reduced, then the thickness of the sealing resin increases, but this affects heat dissipation
Solution Approach 1:
By segmenting the device into multiple chips stacked vertically, the invention creates distributed heat generation points at different heights. This allows heat to dissipate through multiple pathways and prevents heat accumulation, maintaining efficient thermal management even when the overall device height is reduced.
Solution Approach 2:
The vertical stacking arrangement distributes chips in the Z-direction, creating three-dimensional heat dissipation pathways. Heat can conduct through the sealing resin in multiple directions, improving thermal management efficiency while maintaining a compact overall height.
3Ease of manufacture
If lamination regions are absent, then manufacturing is simpler, but adhesion strength between chips decreases
Solution Approach 1:
The invention applies different structural characteristics to different regions: chips are positioned at specific heights with appropriate spacing, creating local lamination regions where adhesion is needed. This localized approach ensures strong bonding at chip interfaces while maintaining manufacturing simplicity through standardized positioning procedures.
4Length of stationary object
If chips are positioned closer together, then device height is reduced, but void formation during manufacturing increases
Solution Approach 1:
By dividing the device into multiple chips positioned at different heights rather than stacking all chips at the same level, the invention creates larger effective bonding areas and more gradual transitions. This segmentation reduces the risk of void formation during manufacturing while achieving compact overall dimensions.
Data Source
AI summary
A semiconductor device includes: a substrate; a first semiconductor chip; a first bonding pad; a second semiconductor chip arranged between the substrate and the first semiconductor chip; a second bonding pad; a first insulating film; a bonding wire that connects the substrate, the first bonding pad, and the second bonding pad; and a sealing resin that seals at least the first semiconductor chip, the second semiconductor chip, and the bonding wire. The second semiconductor chip includes a first surface that faces the substrate, and a second opposite surface. The second surface includes a first bonding region where the second bonding pad and the first insulating film are arranged, and a first lamination region that has a first low-level surface formed lower than a surface of the first insulating film, the first semiconductor chip arranged on or above at least a part of the first low-level surface.