Stacked Chip Package Structure for Compact High-Speed Interconnects
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Solution Overview
Problem
Existing chip packaging technologies result in large-sized packages and low signal transmission rates due to the arrangement of chips and the use of gold wires, which increases the package area by at least 30% and hinders efficient communication between chips.
Innovation Solution
A chip package structure is designed with a stacked configuration where a second chip is placed above a first chip, utilizing a conductive pillar for electrical connection to the package substrate, minimizing space and enhancing signal transmission by reducing the path length and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If chips are packaged separately and then integrated, then multi-functionality is achieved, but the package area increases by at least 30%
Solution Approach 1:
The patent transitions from a planar arrangement of chips to a three-dimensional stacked configuration. Multiple chips are vertically stacked and interconnected through conductive pillars, utilizing the vertical dimension to reduce the horizontal package footprint while maintaining multi-functional capabilities through integrated chip interconnections.
2Reliability
If gold wires are used for electrical connection, then electrical connectivity is achieved, but the signal transmission rate is reduced
Solution Approach 1:
The patent extracts and eliminates the gold wire interconnection method from the chip packaging system. Instead, it employs direct conductive pillar connections between stacked chips, removing the intermediate wire bonding step that limited signal transmission speed and introducing potential points of failure.
Solution Approach 2:
The conductive pillars serve as direct intermediary connection structures between stacked chips, replacing the gold wire mediator. These pillars provide both mechanical support and electrical connectivity in a single integrated structure, enabling shorter signal paths and higher transmission rates while maintaining reliable electrical connections.
3Ease of manufacture
If chips are arranged in a traditional planar configuration, then ease of manufacture is maintained, but the package size becomes large
Solution Approach 1:
The manufacturing process is extended into the vertical dimension through sequential chip stacking. Chips are stacked vertically and connected via conductive pillars, transforming a two-dimensional layout problem into a three-dimensional assembly process that reduces the horizontal package footprint while maintaining manufacturing feasibility through standardized stacking procedures.
4Ease of operation
If the conductive pillar is disposed outside the chip projection area, then ease of connection is improved, but the package area increases
Solution Approach 1:
The conductive pillars are nested within the vertical projection area of the stacked chips, with each pillar positioned to connect corresponding pads on adjacent chips. This nesting arrangement ensures that the connection structures do not extend beyond the chip footprint, maximizing space utilization and minimizing the overall package area while maintaining connection accessibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a more compact package structure with improved signal transmission rates and reduced power consumption, while also providing electromagnetic shielding to prevent interference.
Implementation Method 1
the conductive pillar is provided to realize the electrical connection between the second chip and the package substrate
Implementation Method 2
the chip package structure further includes an electromagnetic shielding layer, and the electromagnetic shielding layer at least covers the second chip as well as sides of the package layer
Data Source
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AI summary
The present disclosure provides a chip package structure, a manufacturing method thereof and an electronic device, and relates to the field of semiconductor technologies, for the purposes of reducing the area of the chip package structure and improving the rate of signal transmission. The semiconductor structure includes a package substrate, a first chip, a conductive pillar and a second chip, wherein the package substrate has a first surface; the first chip is located on the first surface of the package substrate and electrically connected to the package substrate; the conductive pillar is located on the first surface of the package substrate and electrically connected to the package substrate; the second chip is located on a side of the first chip and the conductive pillar away from the package substrate and electrically connected to the conductive pillar; and an orthographic projection of the conductive pillar on the package substrate is located within a range of an orthographic projection of the first chip or the second chip on the package substrate. The chip package structure is configured for connection with a circuit board in the electronic device.