Stacked Chip Package Layout Without TSV Vertical Connections
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Solution Overview
Problem
Current Wafer Level Packaging (WLP) technology does not allow for chip-stacking, leading to complex and costly conventional chip-stacking techniques that require vertical connections using TSV, TGV, TMV, or Wire-bond, complicating the packaging process.
Innovation Solution
A chip packaging method involving forming a stack of chip layers on a carrier substrate, encapsulating them in a molding compound, removing the carrier, and creating a redistribution layer to form a package, without using TSVs or similar vertical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional chip-stacking techniques are used with TSV, TGV, TMV, or Wire-bond for vertical connections, then chip stacking is achieved, but the packaging process becomes complicated and costly
Solution Approach 1:
The patent extracts and eliminates the complex vertical connection technologies (TSV, TGV, TMV, Wire-bond) from the chip stacking process. By using a planar packaging approach where chips are connected through the substrate plane rather than vertical through-silicon vias, the invention removes the problematic vertical connection step while maintaining chip stacking functionality.
Solution Approach 2:
Instead of connecting chips vertically through the substrate thickness (conventional approach), the patent inverts the connection strategy by establishing connections in the lateral plane. The packaging process connects chips through the substrate width rather than depth, fundamentally reversing the connection direction to simplify the overall process.
2Adaptability or versatility
If conventional chip-stacking techniques with vertical connections are used, then chip stacking is achieved, but manufacturing cost increases
Solution Approach 1:
The patent extracts and eliminates the expensive vertical connection technologies (TSV, TGV, TMV, Wire-bond) from the chip stacking process. By using a planar packaging approach where chips are connected through the substrate plane rather than vertical through-silicon vias, the invention removes the costly vertical connection step while maintaining chip stacking functionality.
3Productivity
If Wafer Level Packaging (WLP) is used for streamlined manufacturing, then manufacturing efficiency is improved, but chip-stacking capability is lost
Solution Approach 1:
The patent merges the advantages of Wafer Level Packaging (streamlined manufacturing process) with chip-stacking capability. By performing packaging operations at the wafer level and then stacking the packaged wafers, the invention combines the efficiency of WLP with the functionality of chip stacking, achieving both manufacturing simplicity and vertical integration.
Data Source
AI summary
A method of forming a package comprises forming a stack of chip layers on a carrier. The stack of chip layers including at least a first chip layer over the carrier and a second chip layer over the first chip layer. The first chip layer includes a plurality of first chips facing the carrier and a plurality of chip couplers. The second chip layer includes a plurality of second chips facing the first chip layer. The method further comprises encapsulating the stack of chip layers in a molding compound, removing the carrier to expose the front side of the first chip layer, forming a redistribution layer on the front side of the first chip layer and bumps on the redistribution layer, and dividing the stack of chips and the redistribution layer to form a plurality of the packages. A chip package thus formed include a stack of chips and one or more chip connectors on a singulated redistribution layer.