Stacked Chip Package Pillar Layout for Higher Yield Assembly
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Solution Overview
Problem
Current chip package stack modules face issues with poor yield rates due to exposed conductive pillars and complex manufacturing processes, which increase production costs and hinder mass production.
Innovation Solution
A chip package stack module design featuring vertically stacked chip package units with conductive pillars that have upper and lower pads for secure electrical connections, integrated within a substrate and insulation layer, simplifying the manufacturing process and enhancing structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conductive pillars are exposed and located outside the insulation layer, then the manufacturing process is simpler, but the conductive pillars are easy to get damaged resulting in poor yield rate
Solution Approach 1:
The conductive pillars are pre-formed within the insulation layer during the molding process before final assembly. This preliminary positioning and protection within the insulation matrix prevents damage during subsequent handling and assembly operations, while still allowing for efficient manufacturing.
Solution Approach 2:
The insulation layer serves as a protective cushioning medium that surrounds and protects the conductive pillars from mechanical damage. This beforehand protection is built into the structure during manufacturing, preventing damage before it can occur during assembly or operation.
2Reliability
If conductive pillars are embedded in the insulation layer, then the yield rate improves, but the manufacturing process becomes complicated with two different conductive pins from two different manufacturing processes
Solution Approach 1:
The conductive pillars are integrated directly into the insulation layer during a single molding process, merging the formation of both the insulation structure and the conductive elements into one operation. This eliminates the need for separate processes to create and position conductive pins, reducing overall manufacturing complexity.
Solution Approach 2:
The molding process is designed to perform multiple functions simultaneously: forming the insulation layer, creating through-holes, and positioning conductive pillars all in one operation. This multi-functional approach consolidates what would otherwise require multiple separate manufacturing steps.
3Stability of the object's composition
If whole chip stack is replaced or repaired once there is one defect chip, then the chips are stacked to form a chip stack by molding, but the production cost for manufacturers is increased
Solution Approach 1:
The chip package is divided into separate replaceable modules, each containing its own conductive pillars and insulation structure. This segmentation allows individual modules to be manufactured independently and replaced without affecting other modules, enabling selective replacement rather than whole-stack replacement.
Solution Approach 2:
The modular design enables discarding only the defective module rather than the entire chip stack. The functional modules can be recovered and reused, reducing waste and lowering the effective cost per functional unit produced.
Data Source
AI summary
A chip package unit, a chip package stack module, and a method of manufacturing the chip package stack module are provided. The chip package stack module includes upper and lower chip package units stacked vertically. The chip package unit includes a plurality of conductive pillars each of which has an upper pad and a lower pad respectively on upper and lower ends of the conductive pillar. The upper and lower chip package units are stacked by the lower pads of the upper chip package unit and the upper pads of the lower chip package unit electrically connected with each other. The conductive pillars of the upper chip package unit are electrically connected with the conductive pillars of the lower chip package unit correspondingly so that a memory chip of the upper chip package unit and a memory chip of the lower chip package unit are electrically connected.