Stacked Chip Package With Inclined RDL Routing for Reliable Interconnects

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Solution Overview

Problem

Traditional chip packages with multiple dies integrated on the same side increase area and reliability issues due to wire-bonding, which occupies volume and has lower reliability.

Innovation Solution

A chip package design featuring stacked dies with a molding material having a top, bottom, and inclined portion, a redistribution layer, and an adhesive layer, where the redistribution layer is electrically connected to conductive pads through holes in the molding material, reducing aspect ratios and enhancing reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple dies are integrated on the same side of PCB through wire-bonding, then electrical connection is achieved, but chip package area is dramatically increased

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidchip package area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from planar arrangement of multiple dies on the same PCB side to a three-dimensional stacked configuration where dies are arranged vertically along the Z-axis. This dimensional change allows electrical connections to be achieved through vertical interconnections rather than horizontal wire-bonding, dramatically reducing the chip package area while maintaining electrical connectivity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where multiple dies are stacked vertically, with each die positioned above the previous one. The under-bump metallization layers and conductive structures are nested between the dies, creating a compact vertical integration similar to nested dolls. This nesting approach minimizes the horizontal footprint while accommodating multiple functional dies.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If wire-bonding method is used for electrical connection, then connection is established, but reliability is lower and volume is increased

Engineering Contradiction:
Improveconnection reliabilityVSAvoidchip package volume
Core Design Contradiction:
ReliabilityVSVolume of stationary object

Solution Approach 1:

The patent extracts and eliminates the wire-bonding process from the interconnection methodology. Instead of using wire-bonds to connect dies to the PCB, the invention employs direct solder bump connections and under-bump metallization layers that provide more reliable electrical pathways. This extraction of wire-bonding removes the associated reliability issues and volume occupation.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the mechanical wire-bonding system with a metallurgical bonding system using solder bumps and under-bump metallization. This substitution transitions from mechanical wire attachment to a more robust metallurgical connection that offers higher reliability and reduced volume, as the metallurgical bonds are inherently stronger and more stable than wire bonds.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If molding material covers stacked dies, then protection is provided, but aspect ratio of through hole increases causing redistribution layer breakage

Engineering Contradiction:
Improvedie protectionVSAvoidredistribution layer integrity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent segments the molding material into distinct regions: a first molding material covering the lateral surfaces of the stacked dies, and a second molding material filling the space between the conductive structure and the first molding material. This segmentation allows for optimized material properties and structural support in different regions, reducing stress concentration and preventing redistribution layer breakage while maintaining die protection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different materials and structural properties to different regions of the package. The first molding material provides lateral protection with specific mechanical properties, while the second molding material provides support in the vertical gap region. This local differentiation of material quality optimizes both protection and stress distribution, preventing redistribution layer failure.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11746003B2Chip package
Publication Date: 2023.09.05 XINTEC INC
  • US11746003B2 patent drawing
  • US11746003B2 patent drawing
  • US11746003B2 patent drawing

AI summary

A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.