Stacked Chip Package Using Spacer Conductive Lines
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Solution Overview
Problem
Conventional stacked chip packages face challenges with lengthy processing times, increased package size, and reliability issues due to wire bonding, including bending and protruding phenomena, incomplete resin filling, and unstable electrical connections, especially as the number of stacked chips increases.
Innovation Solution
A stacked semiconductor package structure that eliminates wire bonding by using spacers with patterned conductive lines on stacked semiconductor chips, where a spacer is formed on the side of one chip to facilitate a continuous conductive line connection between chips without cutting or breaking, allowing for reduced package size and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to electrically connect stacked chips and substrate, then electrical connection is achieved, but processing time increases and package size increases
Solution Approach 1:
The patent removes the wire bonding process entirely from the stacked chip package structure. Instead of using separate metal wires to connect chips to the substrate, the invention integrates conductive lines directly into the substrate and chips, eliminating the need for wire bonding and thereby reducing processing time while maintaining electrical connection reliability
Solution Approach 2:
The patent merges the electrical connection function with the substrate and chip structures by forming conductive lines directly within these components. The conductive lines are integrated into the substrate and chip layers, combining the structural and electrical connection functions into a single unified structure, eliminating the need for separate wire bonding steps
2Reliability
If wire bonding is used to electrically connect stacked chips and substrate, then electrical connection is achieved, but package area increases
Solution Approach 1:
The patent extracts the wire bonding component from the package structure, removing the need for additional packaging area to accommodate wire loops and bonding structures. By eliminating wire bonding, the package footprint is reduced while maintaining all necessary electrical connections through integrated conductive lines
Solution Approach 2:
The patent transitions from a three-dimensional wire loop structure to a planar two-dimensional conductive line structure. By forming conductive lines directly within the substrate and chip layers rather than using elevated wire loops, the invention reduces the vertical height requirement and allows for more compact packaging area
3Reliability
If wire bonding is used in stacked chip packages, then electrical connection is achieved, but reliability deteriorates due to bending and protruding phenomena
Solution Approach 1:
The patent removes the wire bonding process and associated materials from the package structure, eliminating the source of bending and protruding defects. By using integrated conductive lines formed within the substrate and chip layers, the invention eliminates wire bonding-related reliability issues while maintaining electrical connection functionality
Solution Approach 2:
Instead of using flexible wire loops that are prone to bending and protruding, the patent inverts the approach by using rigid, planar conductive lines formed directly within the substrate and chip structures. This inversion from three-dimensional wire loops to two-dimensional conductive traces eliminates the mechanical vulnerabilities associated with wire bonding
4Reliability
If wire bonding is used in stacked chip packages, then electrical connection is achieved, but epoxy molding resin filling becomes incomplete
Solution Approach 1:
The patent removes the wire bonding structures that obstruct epoxy molding resin flow and filling. By eliminating the wire loops and bonding structures from the package, the invention allows for complete and uniform resin filling around all chips and substrates, eliminating voids and incomplete filling defects while maintaining electrical connection reliability
5Quantity of substance
If the number of stacked chips increases, then capacity increases, but package size reduction becomes difficult and short between bonding wires occurs
Solution Approach 1:
The patent removes wire bonding entirely from the stacked chip structure, eliminating the risk of shorts between adjacent bonding wires. By using integrated conductive lines within each chip and substrate, the invention allows for increased chip stacking density without the reliability risks associated with closely spaced wire bonds
Solution Approach 2:
The patent transitions from three-dimensional wire loops that occupy vertical space to two-dimensional conductive lines within planar layers. This dimensional change allows for tighter stacking of chips with reduced vertical clearance requirements, enabling increased chip capacity without the short circuit risks associated with elevated wire structures
Data Source
AI summary
Provided is a stacked chip package and a method for forming the same. A spacer is formed on a side of an upper chip. A conductive line is formed on the spacer to electrically connect upper and lower chips. The reliability of the stacked chip package is improved because wire bonding is not used to electrically connect the upper and lower chips. Further, the overall size of the stacked chip package can be reduced as the height of bonding wire loops does not contribute to the overall stacked chip package height.