Stacked Multi-Chip Package Layout for Thermal Balance
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Solution Overview
Problem
Packaged semiconductor devices face thermal imbalance and performance issues when trying to achieve low on-resistance, as increasing die size is constrained by quality issues like die crack, and connecting multiple devices in parallel leads to thermal and power dissipation imbalances.
Innovation Solution
A packaged semiconductor device design where two semiconductor dies with integrated electrical components are stacked and encapsulated in a single package, with conductive elements connecting their terminals to provide a common terminal and mitigate thermal imbalance, without requiring larger die sizes or parallel connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two separate packaged semiconductor devices are connected in parallel to achieve better on-resistance, then the on-resistance performance is improved, but thermal imbalance occurs between the devices
Solution Approach 1:
The invention merges multiple semiconductor dies (first and second semiconductor dies) into a single integrated package structure. The dies are positioned within the same package and connected through internal conductive elements (third conductive element connecting first terminals, first and second conductive elements connecting second terminals). This unified structure ensures common thermal pathways and eliminates the thermal imbalance that occurs when separate packaged devices are connected externally in parallel.
Data Source
AI summary
A packaged semiconductor device is provided, including a first semiconductor die on which a first electrical component is integrated that includes a first terminal at a first surface of the first die and a second terminal at a second surface of the first die, a second semiconductor die similar to the first die, with a first surface of the second die facing the first surface of the first die. A first conductive element on the second surface of the first side electrically connected to the second terminal of the first electrical component, a second conductive element is on the second surface of the second die electrically connected to the second terminal of the second electrical component, and a third conductive element between the first surfaces of the first and the second die. The first terminals of the first and second electrical components are electrically connected through the third conductive element.