Stacked Chip Package Fabrication Preventing Substrate Warping
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Solution Overview
Problem
The challenge in fabricating stacked chip package structures arises from the warping of thin package substrates and chips due to their thin thickness, which complicates subsequent stacking processes.
Innovation Solution
The method involves adhering two chips together and then flipping them onto a substrate for flip chip bonding, ensuring a greater thickness and facilitating easier subsequent processes, while using adhesive layers and baking processes to secure and cure the connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a thin package substrate and thin first chip are used to achieve compactness, then the size of the electronic product is reduced, but the substrate and chip warp after the baking process due to their thin thickness
Solution Approach 1:
The patent combines the first chip and second chip into a stacked configuration before bonding to the substrate. This stacking merges two thin chips into a single unit with increased effective thickness, providing sufficient structural stability during the bonding process while maintaining the compact size benefit of thin individual chips.
Solution Approach 2:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration. By stacking chips vertically before bonding, the solution adds the vertical dimension to increase structural stability without increasing the horizontal footprint, thus preventing warping while maintaining compactness.
2Weight of stationary object
If the package substrate and first chip have thin thickness to achieve light weight and compact design, then the product meets light and slim requirements, but subsequent stacking processes encounter operation difficulties due to warping
Solution Approach 1:
The patent performs the chip stacking operation before the bonding process. By pre-assembling the chip stack while the chips are still flexible and easier to handle, the manufacturing process avoids the difficulty of manipulating warped thin chips during the critical bonding stage, thus improving ease of manufacture.
Solution Approach 2:
The patent merges multiple thin chips into a stacked assembly before bonding. This combination creates a more rigid structure that is easier to handle and position during subsequent manufacturing steps, reducing the operational difficulties associated with manipulating individual thin chips.
3Device complexity
If conventional processes are used with thin substrates and chips, then the manufacturing process is simple, but the warping causes reliability issues in the final stacked package structure
Solution Approach 1:
The patent performs chip stacking before bonding to the substrate. This preliminary action ensures that the chip stack is properly formed and stabilized before the irreversible bonding process, improving the reliability of the final structure without significantly increasing process complexity.
Solution Approach 2:
The patent uses vertical stacking to increase the effective thickness and structural integrity of the chip assembly. This dimensional change improves reliability by preventing warping-induced failures while maintaining a relatively simple manufacturing approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents warping issues and enhances the reliability of the stacked chip package structure by maintaining chip thickness and stability during the fabrication process.
Implementation Method 1
an adhesive layer 240 is formed on the second surface 220b of the first chip 220, and the third surface 230a of the second chip 230 is fixed to the second surface 220b of the first chip 220 through the adhesive layer 240
Implementation Method 2
the second chip 230 is electrically connected to the substrate 210 through the bumps 232 by using a flip chip bonding technique
Implementation Method 3
the first chip 220 is electrically connected to the substrate 210 by using a wire bonding technique
Implementation Method 4
a molding compound 260 is formed on the substrate 210 for encapsulating the first chip 220, the second chip 230, and the bumps 232
Data Source
AI summary
A method of fabricating a stacked type chip package structure is provided. The method includes following steps. First, a substrate, a first chip, and a second chip are provided. A number of bumps are disposed on a surface of the second chip. The second chip is then fixed on a surface of the first chip. Next, the second chip and the first chip on the substrate are turned upside down, and then the second chip is electrically connected to the substrate through the bumps by using a flip chip bonding technique. After that, the first chip is electrically connected to the substrate. Finally, a molding compound is formed on the substrate for encapsulating the first chip, the second chip, and the bumps.