Stacked Chip Package Layout for Shorter Interconnects Without TSVs
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Solution Overview
Problem
Current package-on-package technologies face challenges with signal integrity and power integrity due to long, thin metal lead wires used in wire bonding, which result in poor electrical performance and high process costs, especially at high-speed operations, and through-silicon-via technology is costly and complex.
Innovation Solution
A stacked package design featuring pre-packages with a chip, a first redistribution layer, and first connectors, where the active surface of one pre-package faces the passive surface of another, with connectors electrically connected through the redistribution layer, reducing interconnection length and eliminating the need for through-silicon vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonding is used for interconnection, then the package structure is simple and easy to manufacture, but the electrical performance is poor due to long length and small diameter causing high resistance
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional stacked package architecture. Multiple chips are stacked vertically and interconnected through conductive posts that extend through encapsulation layers, enabling vertical signal transmission paths that significantly reduce interconnection length compared to traditional wire bonding approaches.
Solution Approach 2:
The package is divided into multiple discrete pre-packages, each containing a chip and its associated encapsulation layer with conductive posts. This segmentation allows independent fabrication and testing of individual units before final assembly, improving manufacturing flexibility while maintaining electrical performance through optimized vertical interconnections.
2Reliability
If through-silicon-via technology is used, then the interconnection length is reduced and electrical performance is improved, but the process cost increases
Solution Approach 1:
Conductive posts are formed within the encapsulation layers during the packaging process before chip attachment, rather than requiring post-attachment through-silicon-via formation. This preliminary action simplifies the overall manufacturing process by integrating interconnection structure formation into the encapsulation step, reducing process complexity and cost.
Solution Approach 2:
The encapsulation layer serves as an intermediary medium that not only protects the chip but also houses the conductive posts for interconnection. This dual-function design eliminates the need for separate through-silicon-via structures, reducing process steps while maintaining the electrical performance benefits of short vertical interconnections.
3Ease of operation
If longer metal lead wires are used in wire bonding, then the ease of connection is improved, but the signal transmission time increases and signal integrity deteriorates
Solution Approach 1:
The patent implements vertical stacking architecture where chips are connected through the thickness direction of the package rather than laterally. Conductive posts extend vertically through encapsulation layers to connect chips in different stacks, dramatically reducing the horizontal distance signals must travel and thus reducing transmission delay and maintaining signal integrity.
Data Source
AI summary
The present disclosure relates to a package-on-package, a method of forming and an electronic device including the same. The package-on-package includes at least two pre-packages; each pre-package at least comprises a chip, a first redistribution layer and first connectors; the at least two pre-packages are stacked and interconnected, with the active surface of one pre-package in any two adjacent pre-packages facing the passive surface of the other pre-package, and the first connectors of one pre-package electrically connected with the first redistribution layer of the other pre-package. The first redistribution layer is positioned on an active surface of the chip, the first connectors and the chip are positioned on the same side of the first redistribution layer, and at least some of the first connectors are located on at least one edge side of the chip. Therefore, the stacking/interconnecting of the chip is realized through the first connectors and the first redistribution layer. Compared with the related technology, the length of the electric interconnection is shortened, the electric performance is higher, and through vias are not needed, resulting in lower manufacturing cost.