Stacked Chip Packaging Layout for Thinner Electronic Modules
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Solution Overview
Problem
The miniaturization of electronic devices is hindered by the size of system-level packaging modules, which require multiple substrates to carry a large quantity of chips, leading to increased thickness and occupied space.
Innovation Solution
A packaging module design where all chips are supported by a single substrate layer with a circuit layer, allowing conductive connections between chip layers without additional height, reducing the number of substrates and thickness, and facilitating miniaturization by positioning connection surfaces to minimize conductor impact on module height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple substrates are used to carry a large quantity of chips, then the packaging module can support more chips, but the thickness and occupied space of the packaging module increase
Solution Approach 1:
The patent merges multiple substrate functions into a single substrate layer. The substrate layer simultaneously serves as the support structure for stacking chip layers and as the circuit layer for conductive connections. This consolidation eliminates the need for separate substrate components, reducing the overall thickness while maintaining the capability to carry multiple chips through vertical stacking.
Solution Approach 2:
The patent transitions from a planar arrangement of chips on multiple substrates to a three-dimensional stacked configuration. By stacking chip layers vertically on a single substrate layer, the design utilizes the vertical dimension to accommodate more chips without increasing the horizontal footprint or thickness significantly, as connections are made through vertical conductors rather than horizontal substrate extensions.
2Quantity of substance
If multiple substrates are used to carry chips, then chip carrying capacity increases, but device miniaturization is hindered
Solution Approach 1:
The substrate layer combines support and circuit functions into a single integrated component, eliminating the volume occupied by separate substrate structures. This merging allows the packaging module to maintain high chip carrying capacity while reducing the overall volume required for the support infrastructure.
Solution Approach 2:
The patent implements a nested structure where multiple chip layers are stacked vertically on top of a single substrate layer. This nesting arrangement allows multiple chips to be contained within a compact vertical space, significantly reducing the horizontal occupied space while maintaining high chip density.
3Ease of manufacture
If connection surfaces face away from the substrate layer, then chip connections are simplified, but conductor height and packaging module thickness increase
Solution Approach 1:
The patent inverts the conventional connection surface orientation. Instead of connection surfaces facing away from the substrate layer, they face toward the substrate layer. This inversion allows conductors to connect chips through the substrate layer in a more compact manner, reducing conductor height and overall module thickness while maintaining connection functionality through the substrate's circuit layer.
Data Source
AI summary
A packaging module includes a substrate layer disposed in a stacking manner, and a plurality of chip layers stacked on the substrate layer. The plurality of chip layers include a top chip layer, and the top chip layer is a chip layer furthest from the substrate layer in the plurality of chip layers. The top chip layer includes a first chip, a connection surface of the first chip faces the substrate layer, and the connection surface of the first chip is conductively connected to a chip of an adjacent chip layer by using a first conductor. The connection surface of the first chip faces the substrate layer, so that the first conductor connected to the first chip and another chip does not occupy additional space, to reduce the thickness of the packaging module, and facilitate miniaturization of the packaging module.