Stacked Semiconductor Chip Packaging With Redistribution Pad Bonding
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in efficiently connecting multiple stacked semiconductor chips due to reduced contact area between bonding wires and increased bonding stresses, leading to poor connections and process defects, especially when chip pads are small and densely packed.
Innovation Solution
A semiconductor package design featuring a chip pad portion with a redistribution pad that partially contacts and extends from the chip pad, allowing bonding wires to connect between chip pads and redistribution pads, reducing direct contact stress and minimizing the size of the redistribution pad to maintain a compact package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked vertically with small and densely packed chip pads, then the degree of integration is improved, but the contact area between bonding wires is reduced and bonding stresses increase
Solution Approach 1:
The patent introduces a redistribution pad as an intermediary element between the chip pad and the bonding wire. This redistribution pad serves as a mediator that increases the contact area for bonding wire attachment, thereby improving connection reliability without requiring larger chip pads. The redistribution pad is formed to extend beyond the chip pad boundaries, providing additional surface area for reliable wire bonding while maintaining the compact chip pad design necessary for high integration.
Solution Approach 2:
The patent extends the redistribution pad in the planar direction beyond the chip pad boundaries, effectively utilizing the lateral dimension to increase bonding contact area. This dimensional extension allows the bonding wires to attach to a larger area without increasing the vertical height or compromising the compact chip pad design, thus resolving the contradiction between high integration and bonding reliability.
2Quantity of substance
If chip pads are made small and densely packed to increase integration, then the degree of integration is improved, but bonding stresses concentrate and cause process defects
Solution Approach 1:
The redistribution pad acts as a stress-distributing intermediary between the concentrated chip pad and the bonding wire. By providing a larger attachment area, the redistribution pad disperses the bonding stress over a wider region, preventing stress concentration that would otherwise lead to process defects. This allows the chip pads to remain small and densely packed while maintaining bonding reliability.
Solution Approach 2:
The patent segments the bonding interface into two distinct functional areas: the chip pad region for electrical connection and the redistribution pad region for mechanical bonding. This segmentation allows the chip pads to maintain their small, dense configuration for high integration while the redistribution pad provides a separate, larger area for stress-distributed bonding wire attachment.
3Reliability
If redistribution pad is extended larger to reduce bonding stress, then connection reliability is improved, but package size increases
Solution Approach 1:
The patent applies local quality by extending the redistribution pad only in specific regions where bonding wire attachment is required, rather than uniformly increasing the entire package area. The redistribution pad is strategically positioned to provide sufficient bonding area while minimizing encroachment on the overall package footprint, thus maintaining compact dimensions while improving connection reliability.
Solution Approach 2:
The redistribution pad is extended partially beyond the chip pad boundaries - just enough to provide adequate bonding contact area and stress distribution, but not excessively so as to significantly increase package size. This partial extension achieves the necessary bonding reliability improvement with minimal impact on overall package dimensions.
Data Source
AI summary
A semiconductor package may include: a base layer; first to Nth semiconductor chips (N is a natural number of 2 or more) sequentially offset stacked over the base layer so that a chip pad portion of one side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that partially contacts the chip pad and extends away from the chip pad; and a bonding wire connecting the chip pad of a kth semiconductor chip among the first to Nth semiconductor chips to the redistribution pad of a k−1th semiconductor chip or a k+1th semiconductor chip when k is a natural number greater than 1 and the bonding wire connecting the chip pad of the kth semiconductor chip to a pad of the base layer or the redistribution pad of the k+1th semiconductor chip when k is 1.