Stacked Semiconductor Chip Pad Layout for EDS Impact Isolation
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Solution Overview
Problem
Semiconductor chips experience physical impacts during electrical die sorting (EDS) tests and packaging processes, leading to reduced connection strength and potential damage to pads due to probing traces and external circuit connections.
Innovation Solution
A semiconductor device design with separate bonding pads for external connections and probing pads, incorporating electrostatic discharge protection circuits and input/output circuits in defined spaces, along with a dummy wiring layer to disperse physical impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If semiconductor chips are stacked in a multi-layer structure during packaging, then connection strength between chips is improved, but physical impact from probing and external circuit connections reduces connection strength
Solution Approach 1:
The pad region is segmented into multiple functional zones: a first pad region for bonding pads connected to external circuits, and a second pad region for probing pads used in EDS testing. This segmentation allows different pad types to be treated independently, enabling the bonding pads to maintain strong connections while probing pads can withstand physical impact from testing procedures.
Solution Approach 2:
Different regions of the pad structure are given different properties: the first pad region is designed with characteristics optimized for external circuit connections and bonding strength, while the second pad region is configured to withstand probing physical impact. This local differentiation allows each region to perform its specific function optimally without compromising the other.
2Productivity
If probing pads are used for EDS testing, then electrical die sorting capability is improved, but probing traces reduce connection strength
Solution Approach 1:
The pad structure is divided into separate first and second pad regions, where the second pad region specifically accommodates probing pads for EDS testing. This segmentation isolates the probing function from the bonding function, allowing EDS testing to proceed without compromising the integrity of bonding pads and their connections.
3Reliability
If bonding pads are used for external circuit connections, then electrical connectivity is improved, but physical impact from connections reduces connection strength
Solution Approach 1:
The pad region is segmented into a first pad region dedicated to bonding pads for external circuit connections and a second pad region for probing pads. This segmentation protects the bonding pads from physical impact by isolating them from probing operations, thereby maintaining reliable electrical connectivity.
Solution Approach 2:
The first pad region is specifically designed with properties optimized for external circuit bonding and connection strength, while the second pad region is configured to handle probing operations. This local quality differentiation ensures that bonding pads maintain their connection strength despite external physical impacts.
Data Source
AI summary
A semiconductor device includes: a first semiconductor chip having an upper surface divided into a pixel array region and a connection region, wherein a plurality of pads are disposed in the connection region; and a second semiconductor chip disposed on the first semiconductor chip, wherein the plurality of pads include: a first bonding pad for connection with an external circuit; and a first probing pad adjacent to the first bonding pad and for an electrical die sorting (EDS) test, and wherein the second semiconductor chip includes: a first space overlapping the first bonding pad in a vertical direction and in which at least a portion of an electrostatic discharge protection circuit is formed.