Stacked Chip Test Circuit for Conductive Path Defect Detection
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Solution Overview
Problem
Conventional test circuits and methods fail to effectively detect all types of defects in the conductive paths of stacked chip structures, affecting the reliability and stability of the stacked chip structure product.
Innovation Solution
A test circuit and method that includes a test control circuit, power control circuit, and defect detection circuit to sequentially detect level changes in conductive paths, generating detection results based on comparison signals, and latching results after each defect detection is completed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional test circuits are used, then the test circuit structure is simple, but the detection capability for all types of defects in conductive paths is insufficient
Solution Approach 1:
The test circuit is divided into multiple independent test modules, each responsible for detecting specific types of defects (open circuit, short circuit, inter-path short circuit) through separate test conductive paths. This segmentation enables comprehensive defect detection while maintaining modular simplicity in the overall circuit structure.
Solution Approach 2:
The patent introduces a temporal dimension to the testing process by sequentially activating different test modules through control signals. Instead of requiring all test paths to be active simultaneously, the system activates them one after another, reducing the spatial complexity of the test circuit while maintaining comprehensive detection capability.
2Reliability
If comprehensive defect detection is implemented, then the reliability of stacked chip structure is improved, but the test time increases
Solution Approach 1:
The test circuit employs periodic action by sequentially activating different test modules in repeated cycles. Each cycle tests a specific set of conductive paths, and multiple cycles are executed to cover all possible defect types. This periodic activation pattern enables comprehensive reliability testing while managing test time through systematic progression.
Solution Approach 2:
The test system maintains continuous useful action by ensuring that in each time step, at least one test module is active and performing detection. The sequential activation of test modules ensures no detection activity is wasted, and the system continuously progresses through the testing sequence without idle periods, optimizing the ratio of comprehensive detection to test time.
3Productivity
If multiple conductive paths are tested simultaneously, then the testing efficiency is improved, but the complexity of controlling and detecting each path increases
Solution Approach 1:
The testing system segments the conductive paths into distinct groups, each served by a dedicated test module. This segmentation allows multiple paths to be tested in parallel across different modules while keeping the control and detection logic for each module simple and independent, avoiding the complexity of managing a single monolithic test system.
Solution Approach 2:
Each test module is designed with universal functionality to detect multiple types of defects within its assigned conductive paths. The same test module can identify open circuits, short circuits, and inter-path short circuits by receiving different control signals, eliminating the need for separate specialized detection circuits for each defect type and reducing overall system complexity.
Data Source
AI summary
A test circuit includes: a plurality of conductive paths, a test control circuit, a power control circuit, and a defect detection circuit. The test control circuit is configured to sequentially receive serially input test control signals in response to a test clock signal, and generate and output a plurality of test enable signals in one-to-one correspondence with the plurality of conductive paths; the power control circuit is configured to control, when each of the plurality of test enable signals is in a valid state, a corresponding one of the plurality of conductive paths as a target conductive path to sequentially perform charging and discharging operations; and the defect detection circuit is configured to detect level changes of the plurality of conductive paths separately to generate a plurality of detection identification signals, and generate and output a plurality of detection results in one-to-one correspondence with the plurality of conductive paths.