Stacked Chip Package Layout for Compact PCB Routing and Heat Dissipation
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Solution Overview
Problem
Conventional MOS chip packaging requires large mounting space and routing area on the PCB, leading to a relatively large overall circuit size, which fails to meet packaging requirements.
Innovation Solution
A stacked chip package structure is designed with a wiring layer inside the package to electrically couple two chips vertically, eliminating the need for PCB installation and wiring, and incorporating a heat sink island for efficient heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional individual chip packaging is used, then each chip can be independently packaged and mounted, but the mounting space and routing area on the PCB become large, leading to increased overall circuit size
Solution Approach 1:
The patent implements a stacked chip package structure where multiple chips are vertically stacked and nested within a single package body. The first chip and second chip are positioned at different vertical levels, with connection structures extending between them through the package. This nesting approach allows multiple chips to occupy the same horizontal footprint on the PCB, dramatically reducing the mounting space required compared to conventional side-by-side placement.
Solution Approach 2:
The patent transitions from two-dimensional planar chip arrangement on the PCB to three-dimensional vertical stacking. By utilizing the vertical dimension within the package body, multiple chips can be stacked one above another, connected via internal connection structures. This dimensional change enables high-density integration while maintaining a compact PCB footprint.
2Ease of repair
If multiple chips are mounted separately on PCB, then each chip can be individually replaced and tested, but the routing area and wiring complexity increase significantly
Solution Approach 1:
The patent merges multiple chips into a single integrated package unit with internal electrical connections. The connection structures (conductive vias, wires, or traces) are pre-established within the package during manufacturing, eliminating the need for complex external routing on the PCB. While this reduces wiring complexity, it may impact individual chip replaceability, suggesting a trade-off that prioritizes compactness and simplified external connections.
3Area of stationary object
If chips are closely packed to reduce size, then PCB footprint is minimized, but heat dissipation becomes more difficult and electric-field coupling risks increase
Solution Approach 1:
The patent applies local quality by providing dedicated heat dissipation structures (such as heat sinks or thermal vias) positioned adjacent to each chip within the package. This localized thermal management ensures that each chip has its own heat dissipation pathway, preventing heat accumulation even in closely stacked configurations. The connection structures are also designed with appropriate spacing and insulation to minimize electric-field coupling while maintaining electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces PCB footprint, simplifies circuit wiring, enhances heat dissipation, and improves reliability by minimizing electric-field coupling and breakdown risks.
Implementation Method 1
the plurality of internal pads of the second chip are adhered to the wiring layer using a conductive adhesive to achieve electrical connection
Implementation Method 2
the leadframe comprises a heat sink island, a first surface of the first MOS transistor is formed with the plurality of internal pads, and a second surface of the first MOS transistor is opposite to the first surface and adhered to the heat sink island
Data Source
AI summary
A stacked chip package structure and a method for forming the same are disclosed. The stacked chip package structure includes a lower encapsulant encapsulating a first chip, with a wiring layer on its upper surface and a leadframe on its lower surface, and an upper encapsulant encapsulating a second chip. The internal pads of the first and second chips are disposed opposite each other and electrically coupled via wirings. The wirings connect to the leadframe leads through conductive vias. This structure reduces PCB footprint and wiring space. The heat sink island in the leadframe efficiently transfers heat from both chips to the exterior, improving heat dissipation and device reliability. The packaging method sequentially forms the lower encapsulant, interconnect structure, and upper encapsulant.