Semiconductor Package Interconnect Pillars for Easier 3D Chip Stacking
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Solution Overview
Problem
The complexity of manufacturing semiconductor packages with vertically stacked semiconductor chips using through-electrodes, such as through-silicon vias, hinders the miniaturization and performance enhancement of semiconductor devices.
Innovation Solution
A semiconductor package design that includes a substrate with a redistribution member, an interconnection chip, a via structure, an encapsulant, and pillar structures that simplify the manufacturing process by electrically connecting the redistribution layer, interconnection circuit, and via structure, while also improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-electrodes (through-silicon vias) are used to interconnect vertically stacked semiconductor chips, then electrical connection between chips is achieved, but manufacturing process complexity increases
Solution Approach 1:
The through-electrode structure is segmented into multiple parts: connection bumps on the first chip, pillars extending through the encapsulant, and redistribution layers on the substrate. This segmentation allows each component to be formed and positioned independently, simplifying the overall manufacturing process while maintaining reliable electrical connections between stacked chips.
Solution Approach 2:
An encapsulant is introduced as an intermediary material that fills the space between the first chip and the substrate. The encapsulant provides a medium through which pillars can extend to establish electrical connections, while also offering mechanical support and protection. This intermediary structure simplifies the assembly process by providing a standardized interface between chips and substrate.
2Reliability
If vertically stacked semiconductor chips are assembled with multiple connection structures, then electrical connectivity is improved, but manufacturing difficulty increases
Solution Approach 1:
The substrate serves multiple functions: it provides mechanical support for the stacked chips, acts as a platform for forming connection bumps and pillars, enables electrical redistribution through conductive layers, and provides encapsulation space. This multi-functionality reduces the need for additional separate components, simplifying the overall manufacturing process while maintaining excellent electrical connectivity.
Solution Approach 2:
Connection bumps are formed on the first chip before stacking, and pillars are prepared on the substrate before chip assembly. These preliminary actions allow critical electrical connection structures to be pre-formed and positioned, reducing the complexity of post-assembly operations and improving manufacturing ease while ensuring reliable electrical connectivity.
3Adaptability or versatility
If multiple pillar structures with different configurations are used to connect redistribution layers and via structures, then electrical connection flexibility is improved, but process complexity increases
Solution Approach 1:
Different pillar structures are used at different locations based on local requirements: some pillars extend through the entire encapsulant thickness to connect the first chip directly to the substrate, while other pillars extend only partially to connect via structures. This localized differentiation provides electrical connection flexibility for various circuit configurations while maintaining a relatively simple overall manufacturing process through standardized pillar formation techniques.
Data Source
AI summary
A semiconductor package includes a substrate including a first redistribution member including a first surface and a second surface, and including a first redistribution layer, an interconnection chip below the second surface and including an interconnection circuit electrically connected to the first redistribution layer, a via structure around the interconnection chip and electrically connected to the first redistribution layer, an encapsulant between the second surface and the interconnection chip and the via structure, a first pillar extending through the encapsulant to electrically connect the first redistribution layer and the interconnection circuit, a second pillar extending through the encapsulant to electrically connect the first redistribution layer and the via structure, and connection bumps below the interconnection chip and the via structure, and first and second chip structures on the first surface of the first redistribution member and electrically connected to the first redistribution layer. The first pillar and the second pillar have different shapes.