Stacked-Chip Image Sensor Layout for Faster Pixel Readout
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Solution Overview
Problem
Conventional imaging systems with laterally separated control circuitry and image sensor pixels face limitations in pixel data readout speed and require significant space, making them unsuitable for compact devices like cellular telephones and cameras.
Innovation Solution
A stacked-chip image sensor design featuring a vertical chip stack with image pixels, analog control circuitry, and processing circuitry connected via vertical metal interconnects such as through-silicon vias or microbumps, allowing for efficient communication and reduced lateral footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If control circuitry is laterally separated from image sensor pixels on a silicon semiconductor substrate, then the system can be manufactured using conventional processes, but the lateral footprint of the image sensor chip increases and the readout rate is limited by shared column and row lines
Solution Approach 1:
The patent transitions from a planar lateral arrangement to a three-dimensional stacked architecture. Control circuitry and image sensor pixels are separated into different vertical layers and connected via through-silicon vias (TSVs). This vertical stacking enables high-density interconnection without increasing the lateral footprint, as multiple signal paths can be routed through the thickness of the substrate rather than competing for lateral space.
Solution Approach 2:
The patent divides the monolithic substrate into separate functional layers: an image sensor pixel layer and a control circuitry layer. Each layer can be independently optimized and manufactured, then bonded together through TSV interconnections. This segmentation allows dedicated vertical interconnects for each pixel column, eliminating the need for shared lateral metal lines and enabling higher parallel readout rates.
2Ease of manufacture
If control circuitry is laterally separated from image sensor pixels, then manufacturing is simplified, but the readout rate is limited by shared column and row lines
Solution Approach 1:
By moving interconnections to the vertical dimension through TSVs, the system enables multiple independent data paths from different pixel columns to simultaneously access control circuitry. This eliminates the bottleneck of shared lateral metal lines, as each column can have its own dedicated vertical interconnect, thereby increasing parallel readout capacity and overall productivity.
Solution Approach 2:
Through-silicon vias serve as intermediary vertical conduits that bridge the image sensor pixel layer and control circuitry layer. These TSVs provide dedicated high-speed data paths that bypass the limitations of lateral metal line sharing, enabling faster and more efficient pixel-to-control-circuitry communication without compromising manufacturing simplicity.
3Ease of manufacture
If control circuitry is integrated on the same substrate as image sensor pixels, then manufacturing is easier, but significant space is required accommodating the control circuitry
Solution Approach 1:
The patent relocates control circuitry from the lateral plane to a separate vertical layer, connected via TSVs. This three-dimensional integration allows the chip area to be determined primarily by the pixel array dimensions, while control circuitry occupies the vertical space above or below the pixels. This dramatically reduces the lateral footprint compared to planar integration where control circuitry must be distributed across the substrate.
Solution Approach 2:
The patent implements a nested vertical structure where the control circuitry layer is positioned above or below the image sensor pixel layer, with TSVs providing inter-layer connectivity. This nested arrangement allows both functional layers to coexist within the same vertical column footprint, maximizing space utilization and minimizing the overall chip area required for a given pixel resolution.
Data Source
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AI summary
A stacked-chip image sensor comprises a first semiconductor substrate having opposing first and second surfaces, wherein the first semiconductor substrate includes image sensor pixels that are configured to receive image light through the first surface, a second semiconductor substrate coupled to the second surface, wherein the second semiconductor substrate includes control circuitry for operating the image sensor pixels to capture image data and a plurality of vertical conductive interconnects that couple the control circuitry to the array of image sensor pixels through the second surface, wherein each of the vertical conductive interconnects couples a plurality of pixels arranged in a line to the control circuitry.