Stacked Chip Structure with Patterned Polymer Layers
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Solution Overview
Problem
The existing stacked chip structures face challenges with heat dissipation efficiency due to the use of underfill materials that are poor conductors, and the fine-pitch solder bumps are prone to overflowing during the heating process, leading to circuit shortages and popcorn effects when air is trapped between wafers.
Innovation Solution
The introduction of patterned polymer layers between chips, which enhance bonding strength and prevent solder bump overflow, while also allowing for heat dissipation through trenches that expose the conductive layers, eliminating the need for underfill and enabling bonding under atmospheric conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If underfill is used to protect solder bumps, then reliability is improved, but heat dissipation efficiency deteriorates because underfill is a bad conductor
Solution Approach 1:
The patent removes the underfill material from the stacked chip structure, eliminating the thermal insulation problem entirely. The chips are bonded directly to each other through solder bumps without any intermediate underfill layer, allowing heat to conduct efficiently through the solder bumps and conductive plugs without being blocked by thermally insulating underfill material.
2Strength
If heating is applied to soften solder bumps for connection, then bonding strength is improved, but solder bumps overflow onto adjacent solder bumps causing circuit shortage
Solution Approach 1:
The patent performs preliminary actions by forming a protective polymer layer on each chip surface before stacking, and creating conductive plugs that extend beyond the chip surfaces. These preliminary structures prevent solder bump overflow during heating while maintaining bonding strength, eliminating the need for vacuum bonding and underfill protection.
3Area of stationary object
If fine-pitch solder bumps are used to reduce chip area, then area is reduced, but solder bumps are more prone to overflow during heating
Solution Approach 1:
The patent forms protective polymer layers on chip surfaces and extends conductive plugs beyond chip edges before stacking. These preliminary structures create physical barriers that prevent fine-pitch solder bumps from overflowing onto adjacent bumps during heating, maintaining circuit integrity while enabling fine-pitch designs.
Solution Approach 2:
The patent applies different properties to different regions: the polymer layer provides protection where solder bumps are located, while the extended conductive plugs provide localized thermal and electrical pathways. This localized quality enhancement allows fine-pitch solder bumps to maintain their small size without sacrificing reliability.
4Reliability
If vacuum bonding is used to prevent air pockets, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming protective polymer layers and extending conductive plugs before stacking. These preliminary structures prevent air pocket formation and enable atmospheric pressure bonding, eliminating the need for complex vacuum bonding equipment and processes while maintaining reliability.
5Strength
If heating is applied to bond chips, then bonding strength is improved, but popcorn effect occurs when air is trapped between wafers
Solution Approach 1:
The patent forms protective polymer layers and extends conductive plugs before stacking as preliminary actions. These structures prevent air pocket formation between chips, eliminating the source of popcorn effect during heating while maintaining bonding strength through the solder bumps and polymer layers.
Solution Approach 2:
The patent converts the potential harm of trapped air causing popcorn effect into a benefit by using the extended conductive plugs and polymer layers to actively prevent air trapping. The preliminary structures serve as barriers that guide air escape paths, transforming the heating process from potentially harmful to beneficial without sacrificing bonding strength.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves heat dissipation efficiency and bonding reliability by preventing solder bump overflow and eliminating the need for underfill, while reducing manufacturing costs by allowing bonding under atmospheric conditions rather than vacuum.
Implementation Method 1
an electroplating process for the high-aspect-ratio via 12 is implemented to fill a conductive material 20 into the via 12
Implementation Method 2
the method of connecting the solder bumps 30 of each of the chips 10 to the conductive material 20 of the adjacent chips 10 mostly includes heating the solder bumps 30 of each of the chips 10, such that the solder bumps 30 of each of the chips 10 are softened
Data Source
AI summary
A fabrication method of a stacked chip structure is provided. Firstly, a first conductive layer is formed on a first surface of a wafer. Afterwards, a first patterned polymer layer is formed on the first conductive layer, and a second patterned polymer layer is formed on a second surface of the wafer. Next, a second conductive layer is electroplated on the first conductive layer and is heated to form a number of solder bumps. After that, the wafers are stacked on a substrate structure. The first patterned polymer layer disposed on a first wafer of the wafers is correspondingly connected to the second patterned polymer layer on a second wafer of the wafers. The present invention is suitable for the stacked chip structure connected by the fine-pitch solder bumps. Besides, the fabrication of the present invention is relatively simplified.