Stacked Chip Packaging Structure With RDLs for Compact Integration
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Solution Overview
Problem
The increasing number and types of devices on chip packaging structures result in larger space occupation and volume, necessitating a reduction in size and improving structural integrity.
Innovation Solution
A chip packaging structure comprising a first and second redistribution layer with a packaging layer sandwiched between, embedding stacked chip wafers for electrical connections, and optionally including supporting members for enhanced stability and conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chip wafers and devices are stacked on a substrate using traditional solder ball welding, then the functionality and device types increase, but the volume and space occupation of the chip packaging structure increase significantly
Solution Approach 1:
The patent transitions from traditional planar substrate mounting to a three-dimensional stacked architecture using redistribution layers (RDL) as intermediate connection platforms. Chip wafers are mounted vertically stacked through multiple RDL layers rather than spreading horizontally on a single substrate, effectively utilizing the Z-dimension to reduce the footprint and overall volume of the packaging structure while maintaining high device density and functionality.
2Adaptability or versatility
If more chip wafers are stacked to increase functionality, then the device capability improves, but the structural integrity and stability of the packaging structure deteriorate
Solution Approach 1:
The packaging structure is segmented into multiple discrete functional layers including substrate, first RDL, chip wafers, second RDL, and encapsulation layer. Each layer performs a specific function and can be independently optimized. The redistribution layers act as intermediate connection platforms that distribute mechanical and electrical loads, preventing stress concentration and maintaining structural integrity as the number of stacked chip wafers increases.
Solution Approach 2:
The patent employs composite material structures combining different materials with complementary properties: conductive materials for RDL interconnections, encapsulation materials for mechanical protection and environmental sealing, and substrate materials providing foundational support. This multi-material composite approach enhances overall structural stability while accommodating the increased complexity of stacked chip configurations.
3Ease of manufacture
If traditional solder ball welding is used to mount chip wafers on substrate, then the manufacturing process is simple, but the electrical connection efficiency and signal transmission performance are limited
Solution Approach 1:
Redistribution layers (RDL) are introduced as intermediary structures between the substrate and chip wafers, and between stacked chip wafers themselves. These RDL layers provide dedicated electrical pathways that improve signal transmission efficiency and reduce interference compared to direct solder ball connections. The RDLs act as intermediate platforms that facilitate both electrical interconnection and mechanical support in the stacked architecture.
Data Source
AI summary
This application discloses a chip packaging structure, an electronic device, and a preparation method. The packaging structure includes: a first redistribution layer, chip wafers, a second redistribution layer, and a packaging layer. The first redistribution layer and the second redistribution layer are electrically connected to each other. The packaging layer is sandwiched between the first redistribution layer and the second redistribution layer. At least two stacked chip wafers are embedded in the packaging layer. Any two adjacent chip wafers are electrically connected to each other, and any of the chip wafers is electrically connected to at least one of the first redistribution layer and the second redistribution layer.