Stacked Semiconductor Packaging with RDL and Conductive Pillars
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Solution Overview
Problem
Existing semiconductor package structures face challenges with high manufacturing costs and complexity due to copper-copper (Cu—Cu) bonding technology, which requires high temperature and time for inter-diffusion, leading to difficulties in reducing production costs and increasing yield.
Innovation Solution
The semiconductor package structures utilize a redistribution layer and bump structures or through vias to electrically couple semiconductor components, eliminating the need for Cu—Cu bonding and allowing for reduced manufacturing complexity and cost, while enabling flexible integration of different chip sizes and generations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper-copper (Cu—Cu) bonding technology is utilized to provide interconnections between semiconductor dies, then reliable electrical connections are achieved, but high temperature and time for inter-diffusion are required, raising manufacturing costs and leading to difficulties in the manufacturing process
Solution Approach 1:
The patent introduces a redistribution layer as an intermediary component between semiconductor dies, replacing direct Cu-Cu bonding. This redistribution layer serves as a mediator that establishes electrical connections without requiring high-temperature inter-diffusion processes, thereby maintaining connection reliability while simplifying manufacturing
Solution Approach 2:
The patent replaces the thermal-mechanical Cu-Cu bonding process with an alternative electrical connection method using redistribution layers and conductive structures. This substitution eliminates the need for high-temperature processing and extended diffusion time, significantly easing manufacturing while maintaining electrical connection integrity
2Reliability
If copper-copper (Cu—Cu) bonding technology is utilized to provide interconnections between semiconductor dies, then electrical connections are established, but enough time for inter-diffusion is required, raising manufacturing costs
Solution Approach 1:
The redistribution layer acts as an intermediary that enables electrical connections without requiring extended inter-diffusion time. By mediating the connection between dies, it eliminates the time-consuming thermal diffusion process while maintaining reliable electrical connectivity
Solution Approach 2:
The patent employs preliminary actions by pre-configuring the redistribution layer with necessary conductive pathways and structures before final die assembly. This preliminary preparation eliminates the need for time-consuming inter-diffusion processes during manufacturing, reducing both time and cost
3Area of stationary object
If smaller package structures are implemented to take up less space, then space efficiency is improved, but manufacturing complexity and cost increase due to Cu—Cu bonding requirements
Solution Approach 1:
The patent transitions from planar Cu-Cu bonding approaches to a vertical stacking architecture enabled by redistribution layers. This dimensional change allows multiple semiconductor dies to be stacked in three dimensions, reducing the footprint area while the redistribution layer simplifies the manufacturing process by eliminating complex inter-diffusion requirements
Data Source
AI summary
A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.