Stacked Semiconductor Chip Packaging With Recessed Wire Terminals
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Solution Overview
Problem
In semiconductor device manufacturing, existing methods face challenges in efficiently exposing wire ends from sealing resin while maintaining surface flatness and preventing wire distortion, which can lead to connection failures and increased material costs.
Innovation Solution
A semiconductor device configuration where wires extend vertically through a sealing resin with recesses formed on its surface, allowing terminals to be buried within the resin and connected to the wires, enabling reliable exposure and connection to build-up layers without polishing the resin and wires together, thus reducing wire elongation and material requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the sealing resin is polished to expose the wires from the surface, then the wires can be connected to the build-up layer or printed circuit board, but the surface flatness deteriorates and wire distortion occurs
Solution Approach 1:
The patent divides the sealing resin surface into different regions: a first surface region where wires are exposed for connection, and a second surface region that remains flat for mounting. This segmentation allows the resin to be polished selectively in different areas, achieving both wire exposure and surface flatness in各自 regions without compromising the other.
2Ease of manufacture
If the sealing resin is polished to expose the wires, then connection to build-up layer is enabled, but wire elongation and distortion increase leading to connection failures
Solution Approach 1:
By segmenting the polishing process into selective areas, the patent minimizes the polished region to only where wires need exposure. This reduces the mechanical stress and distortion applied to the wires, maintaining their structural integrity and connection reliability while still achieving the necessary wire exposure for connection.
Solution Approach 2:
The patent applies different surface treatments to different locations: the first surface region undergoes polishing to expose wires, while the second surface region maintains its original flatness. This local differentiation ensures that wire exposure is achieved only where needed, preserving wire quality and connection reliability in the exposed regions.
3Ease of manufacture
If conventional polishing is used to expose wires, then wire connection is achieved, but material costs increase due to wire elongation and higher material requirements
Solution Approach 1:
The segmented polishing approach limits the polished area to only where wire exposure is necessary, reducing the overall amount of resin removed and wire elongation. This minimizes material waste and reduces the quantity of wire material needed, thereby lowering material costs while achieving the required wire exposure for connection.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a plurality of stacked semiconductor chips each of which has a first surface having an electrode formed thereon, a plurality of wires each of which has one end portion connected to each of the electrodes of the plurality of semiconductor chips and extends in a stacking direction of the semiconductor chips, a sealing resin that covers the plurality of semiconductor chips, has a second surface having recesses formed therein, and is formed so that the other end portions of the plurality of wires and the recesses overlap each other when viewed from the stacking direction, and a plurality of terminals that is provided so as to fill the recesses, each of which has one end portion connected to the other end portion of each of the plurality of wires and has the other end portion exposed from the sealing resin.