Stacked Semiconductor Chip Wire Bonding via Relay Pad Layer
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Solution Overview
Problem
In semiconductor devices with stacked chips, the mismatch between the precision of electrode pads on the chips and the lower precision of connection pads on the wiring substrate leads to increased wire stretching angles, resulting in longer wire lengths and larger substrate sizes, which increases manufacturing costs and reduces reliability due to potential wire interference with chip edges.
Innovation Solution
The configuration of the semiconductor device includes identical upper and lower semiconductor chips with specific pitch relationships between independent and common electrode pads, where the first pitch is larger than the second pitch, and both are larger than the connection pad pitch on the substrate, allowing for one-to-one and two-to-one coupling to reduce wire stretching angles and substrate size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If connection pads are arranged with wider intervals to accommodate low-precision formation processes, then manufacturing precision requirements are relaxed, but wire stretching angle increases leading to longer wire lengths
Solution Approach 1:
The patent introduces a relay pad layer between the semiconductor chip electrode pads and the wiring substrate connection pads. This intermediate layer adds a dimensional level to the connection architecture, allowing the wire to connect to the relay pad first (which is positioned closer to the chip) and then extend to the connection pads. This dimensional addition enables shorter wire lengths while accommodating the wider pitch of connection pads formed by low-precision processes.
Solution Approach 2:
The relay pad acts as an intermediary element that mediates the connection between the electrode pads and connection pads. By introducing this intermediate connection point, the system can accommodate the mismatch between the precise electrode pad positions and the less precise connection pad positions without requiring excessively long wires. The relay pad absorbs the positional discrepancy and enables efficient electrical connection.
2Reliability
If connection pads are positioned distant from chip edges to reduce wire stretching angle, then wire interference with chip edges is suppressed improving reliability, but substrate size increases leading to higher manufacturing costs
Solution Approach 1:
By adding the relay pad layer as an intermediate dimension, the system can position connection pads at optimal locations on the substrate without being constrained by the need to maintain large distances from chip edges. The relay pad handles the connection function close to the chip, allowing connection pads to be positioned more efficiently on the substrate, thus reducing overall substrate size while maintaining reliability.
Solution Approach 2:
The connection function is segmented into two parts: the relay pad near the chip that handles the critical connection function, and the connection pads on the substrate that can be optimally positioned. This segmentation allows the substrate layout to be optimized for size while the relay pad ensures reliable connections without wire interference issues.
3Adaptability or versatility
If two independent connection pads are provided for selective wire connection, then independent electrode pads can be connected separately, but the row of connection pad group becomes larger in length
Solution Approach 1:
Multiple independent electrode pads from different chips are merged and connected to a single shared relay pad. This combining approach reduces the number of separate connection pads needed on the substrate, as one relay pad can serve multiple electrode pads. The connection pad group length is thereby reduced while maintaining the selective wire connection capability, as wires can still be selectively routed to the shared relay pad based on which electrode pads need connection.
Data Source
AI summary
A semiconductor chip at least includes a row of first electrode pad group, which includes at least one first independent electrode pad and multiple first common electrode pads. The interval between the first independent electrode pad and an electrode pad adjacent thereto is defined as “first pitch”, and the interval between adjacent electrode pads making up the multiple first common electrode pads is defined as “second pitch”. The first pitch is determined to be larger than the second pitch.