Stacked Logic Memory Chip Thermal Insulation via Resin Layer

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Solution Overview

Problem

The integration of a logic chip with memory chips in a semiconductor device leads to increased heat generation, which can cause malfunction or reliability deterioration of the memory chips due to insufficient heat management.

Innovation Solution

The implementation of a semiconductor device architecture that includes a redistribution layer with a resin layer of lower thermal conductivity between the logic chip and memory chips, along with the use of a spacer resin without fillers to enhance heat insulation, and a filler-containing sealing resin to improve thermal conductivity and structural strength, effectively increasing the distance between the logic chip and memory circuits to reduce heat transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a logic chip is integrated with memory chips in a stacked package, then functionality and memory capacity are improved, but heat generation increases causing memory chip malfunction and reliability deterioration

Engineering Contradiction:
ImprovefunctionalityVSAvoidmemory chip reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces a resin layer as an intermediary substance between the logic chip and memory chips. This resin layer has lower thermal conductivity compared to the chips, creating a thermal barrier that reduces heat transfer from the logic chip to the memory chips, thereby protecting memory reliability while maintaining functional integration

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies different materials with different thermal properties to different regions of the package. The resin layer is specifically positioned where heat transfer needs to be blocked, while other areas may use different materials optimized for their specific functions, creating a heterogeneous thermal management structure

Inventive Principle:
Principle #3Local quality

2Reliability

If a resin layer with lower thermal conductivity is inserted between logic chip and memory chips, then heat transfer to memory chips is reduced, but device complexity increases

Engineering Contradiction:
Improvememory chip reliabilityVSAvoidpackage structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The resin layer serves multiple functions simultaneously: it acts as a thermal barrier to reduce heat transfer, provides mechanical bonding between chips, and fills the gaps between stacked components. By combining thermal management and structural functions in a single element, the patent avoids increasing overall device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively suppresses memory chip malfunction and reliability deterioration by reducing heat transfer from the logic chip to the memory chips, enhancing the semiconductor device's performance and reliability.

Implementation Method 1

a resin layer of lower thermal conductivity between the logic chip and memory chips

Methodology Applied
Scientific EffectThermal insulation: Thermal Insulation

Implementation Method 2

a filler-containing sealing resin to improve thermal conductivity and structural strength

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS10497688B2Semiconductor device having stacked logic and memory chips
Publication Date: 2019.12.03 KIOXIA CORP
  • US10497688B2 patent drawing
  • US10497688B2 patent drawing
  • US10497688B2 patent drawing

AI summary

A semiconductor device according to an embodiment includes a first memory chip having a first front surface and a first back surface and having a first memory circuit provided on the first front surface side; a second memory chip having a second front surface and a second back surface facing the first front surface, having a second memory circuit provided on the second front surface side, and being electrically connected to the first memory chip; and a logic chip having the first memory chip provided between the logic chip and the second memory chip, having a third front surface and a third back surface, having a logic circuit provided on the third front surface side, and being electrically connected to the first memory chip.