Stacked Chip Alignment Using Resistance Measurement
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Solution Overview
Problem
Current methods for aligning stacked chips in integrated circuit manufacturing are limited, as they do not allow for individual chip alignment, which restricts the selection of optimal chips for maximum yield and do not ensure proper electrical connection, and existing magnetic alignment methods lack directionality and require magnetic materials.
Innovation Solution
The method employs exposed metal bumps on one chip and etched metal troughs on another, using resistance measurements to determine alignment quality and direction, ensuring physical alignment and connectivity by measuring resistance between sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If physical alignment process is used to align entire wafers, then alignment is achieved, but the number of good stacked chips is limited due to spatial alignment requirements
Solution Approach 1:
The patent divides the alignment process from wafer-level to individual chip-level alignment. Each chip is aligned separately using resistance measurements between corresponding pads, allowing selection of any good chip from either wafer regardless of spatial position. This segmentation enables maximum yield by independently matching good chips from both wafers.
2Productivity
If individual chip alignment is implemented, then maximum yield can be achieved by selecting all good chips, but the complexity of the alignment process increases
Solution Approach 1:
The patent replaces complex mechanical alignment systems with an electrical resistance measurement system. Instead of using sophisticated mechanical positioning devices, the system uses simple resistance measurements between corresponding pads to determine alignment quality and guide the alignment process, significantly reducing system complexity.
Solution Approach 2:
The patent implements a feedback mechanism where resistance measurements provide real-time information about alignment quality. The measured resistance values are compared against expected values, and this feedback guides adjustments to achieve proper alignment, simplifying the overall process through intelligent control.
3Manufacturing precision
If magnetic forces are used to align chips, then alignment in X and Y directions is achieved, but magnetic materials are required and electrical connection quality cannot be ensured
Solution Approach 1:
The patent replaces magnetic alignment forces with an electrical resistance-based alignment system. Instead of using magnetic materials and magnetic fields, the system uses resistance measurements between corresponding pads to achieve and verify alignment, eliminating the need for magnetic materials and ensuring proper electrical contact is achieved.
4Productivity
If high yielding design is placed on one stacked chip to mitigate alignment issues, then yield is improved, but the complexity of design that can be placed on that chip is limited
Solution Approach 1:
The patent enables independent evaluation and selection of individual chips from each wafer through resistance measurements. This allows complex designs to be distributed across multiple chips that are individually verified, rather than concentrating high-yielding design constraints on a single chip. Each chip can be assessed and selected independently based on its own performance characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise alignment and electrical connection of chips, enabling the selection of optimal chips for maximum yield and complex design integration while avoiding the need for magnetic materials and ensuring proper electrical contact.
Implementation Method 1
A resistance measurement will be taken to determine the quality of the alignment. These bumps and troughs can be used to physically align the two chips using a pattern on each chip.
Data Source
AI summary
The present invention relates to a method of aligning stacked chips wherein the apparatus and method utilize bumps in the form of exposed metal lines on a first chip. The present invention further relates to taking a resistance measurement to determine a quality of alignment wherein the resistance measurement indicates a direction in which the first chip and the second chip are misaligned.