Stacked Chip Resistor Layout for High-Density Semiconductor Circuits
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Solution Overview
Problem
As semiconductor devices become increasingly highly integrated, the area occupied by resistor elements grows, leading to space constraints and potential failures due to heat generation and degradation of adjacent components.
Innovation Solution
The semiconductor device incorporates stacked chips with vertically or horizontally arranged resistor patterns that share layout space with peripheral circuits, reducing area consumption and manufacturing complexity, while allowing for increased line width without resistance loss, thus minimizing heat-related failures and enhancing integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If resistor elements are used in highly integrated semiconductor devices, then circuit functionality is achieved, but the area occupied by resistor elements increases
Solution Approach 1:
The patent transitions from planar resistor layouts to three-dimensional stacked chip architecture. Resistor elements are distributed across multiple vertically stacked chips, utilizing the vertical dimension to reduce the footprint area on each individual chip while maintaining total resistance functionality through series connections between chips.
Solution Approach 2:
The patent divides the semiconductor device into multiple separate chips, each containing a portion of the total resistance. These segmented resistor elements are then connected in series through vertical stacking, achieving the required total resistance while distributing the area occupancy across multiple smaller chip footprints.
2Measurement precision
If resistor elements are increased in area to achieve higher resistance values, then resistance precision is improved, but heat generation increases causing failures
Solution Approach 1:
The patent uses vertical stacking to distribute resistor elements across multiple chips in the vertical dimension. This allows achieving high total resistance through series connection of multiple smaller resistance elements, reducing the area and heat generation of individual elements while maintaining precision through their cumulative effect.
Solution Approach 2:
The patent creates multiple copies of smaller resistor elements across different chips, connecting them in series. Each copied element generates less heat individually, but their series combination achieves the required total resistance with improved precision and reduced heat-related failures.
3Area of stationary object
If resistor elements are distributed across multiple chips, then area consumption is reduced, but device complexity increases
Solution Approach 1:
The patent combines multiple chips containing resistor elements into a single integrated stacked structure. The internal connections between chips are merged into a unified three-dimensional assembly, reducing the overall footprint area while managing complexity through integrated packaging and interconnection techniques.
Data Source
AI summary
A semiconductor device includes a first pad defined on one surface of a first chip; a second pad defined on one surface of a second chip which is stacked on the first chip, and bonded to the first pad; a first resistor element defined in the first chip, and coupled to the first pad; and a second resistor element defined in the second chip, and coupled to the second pad.