Stacked Chip Rewiring Layer for Shorter Interconnect Paths

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Solution Overview

Problem

The integration of semiconductor chips results in longer wirings between electrode pads, leading to increased parasitic capacitance and inductance, which in turn increases power consumption and degrades frequency characteristics.

Innovation Solution

An integrated electronic component design featuring a rewiring layer with insulator-based interlayer connection conductors that connect electrode pads on opposing surfaces of chips, reducing the length of conductors and minimizing parasitic effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If components are integrated on the same flat surface using conventional rewiring, then integration is achieved, but wiring length increases leading to increased parasitic capacitance and inductance

Engineering Contradiction:

Improveintegration capabilityVSAvoidwiring length

Core Design Contradiction:

Adaptability or versatilityVSLength of moving object

Solution Approach 1:

The patent transitions from planar integration to three-dimensional integration by stacking chips vertically. The first chip is mounted on the molded resin, and the second chip is mounted on the rewiring layer that is itself mounted on the molded resin containing the first chip. This vertical stacking arrangement dramatically reduces wiring length compared to planar placement while achieving full integration functionality.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces a molded resin as an intermediary medium that contains the first chip and provides a mounting substrate for the rewiring layer. The rewiring layer acts as another intermediary, providing electrical connections and a mounting surface for the second chip. These intermediary structures enable compact three-dimensional integration while managing wiring length.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If wiring length is reduced to minimize parasitic effects, then frequency characteristics improve, but integration complexity increases

Engineering Contradiction:

Improvefrequency characteristicsVSAvoidintegration structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the integrated component into distinct functional segments: the first chip containing input electrode pads, the molded resin encapsulation, the rewiring layer with intermediate electrode pads and connection conductors, and the second chip with output electrode pads. This segmentation allows each layer to be optimized independently while maintaining overall integration, achieving short wiring lengths without excessive complexity.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS20230420316A1Integrated Electronic Component

Publication Date: 2023.12.28 NT T INC

AI summary

An integrated electronic component includes a lower chip having electrode pads, a molded resin, a rewiring layer, and an upper chip having electrode pads. The rewiring layer has electrode pads that are formed on the lower surface of an insulator and are connected to the electrode pads, electrode pads that are formed on the upper surface of the insulator and are connected to the electrode pads, and interlayer connection conductors that are formed in the insulator and connect the electrode pads and the electrode pads. The electrode pads and the electrode pads are disposed to face each other.