Stacked Semiconductor Chip Selection Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices with stacked structures face challenges in efficient chip selection, leading to increased area overhead and complex management of unique chip addresses, particularly when the number of stacked semiconductor chips doubles.
Innovation Solution
The semiconductor device employs arithmetic circuits on each stage to perform a predetermined arithmetic operation on an input selection signal, with determination circuits determining whether the signal matches a specific bit string, allowing for chip selection without the need for unique addresses and reducing the number of required through electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of through electrodes is increased to support doubled number of stacked semiconductor chips, then the chip selection capability is improved, but the area overhead increases
Solution Approach 1:
The patent segments the chip selection function into multiple stages, where each stage processes a portion of the selection signal. Instead of using one large set of through electrodes to directly select among all chips, the selection process is divided into sequential stages, each handling a subset of chips. This segmentation reduces the number of through electrodes needed at any single stage while maintaining the ability to select among all chips in the stack.
Solution Approach 2:
The patent introduces a temporal dimension to the chip selection process by using multiple stages processed sequentially. Instead of selecting chips spatially in parallel through multiple through electrodes, the selection occurs across time stages, where each stage narrows down the selection scope. This dimensional transformation from spatial parallel selection to temporal sequential selection reduces the area overhead.
2Measurement precision
If unique chip addresses are stored in memory or register for each semiconductor chip, then chip identification is improved, but the device complexity and management difficulty increase
Solution Approach 1:
The patent implements a self-service mechanism where each chip automatically determines its own selection status through local arithmetic operations on the selection signal. Instead of requiring external storage of unique addresses or complex management systems, each chip independently computes whether it should be selected by performing arithmetic operations (such as multiplication or addition) on the received selection signal and comparing the result to a locally stored constant. This eliminates the need for centralized address management while maintaining precise chip identification.
3Reliability
If the power supply capacity is increased to support more through electrodes, then the chip selection signal transmission is improved, but the area overhead and power consumption increase
Solution Approach 1:
The patent segments the signal transmission path into multiple stages, where each stage processes a subset of chips. This segmentation reduces the number of active through electrodes and associated power supply circuits needed at any given time, thereby reducing overall power consumption while maintaining reliable signal transmission for the selected chip.
Solution Approach 2:
The patent employs periodic action by sequentially activating different stages of the selection process. Instead of maintaining all through electrodes and power supply circuits active simultaneously, the system periodically activates only the necessary stages for the current selection operation, reducing average power consumption while ensuring reliable signal transmission when needed.
Data Source
AI summary
In a semiconductor device, an arithmetic circuit of a chip on a first stage performs a predetermined arithmetic operation on an input N-bit (N=4) selection signal. Similarly, an arithmetic circuit of each of chips on second and subsequent stages among chips on a total of M stages (M>N≥2, M=16) performs a predetermined common arithmetic operation on an operation result of the arithmetic circuit of the chip on the preceding stage. A determination circuit provided in each chip performs a predetermined common logic operation on a bit string of the N-bit signal, which is the operation result of the corresponding arithmetic circuit, thereby determining whether it is the chip selected by the selection signal.