Stacked Semiconductor Chip Selection via Through-Line Cycle
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Solution Overview
Problem
Existing semiconductor device technologies face challenges in efficiently selecting and designating multiple semiconductor chips using through-lines, as they often require a large number of through-lines to distinguish a limited number of chips, leading to inefficiencies in chip identification and designation.
Innovation Solution
The semiconductor device employs a configuration of through-lines arranged in a predetermined simple directed cycle, grouping them into coprime sets to create a larger number of distinguishable combinations using a smaller number of through-lines, allowing for efficient chip selection and designation by utilizing a unique combination of bank addresses and internal signal generation circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large number of through-lines are used to distinguish multiple semiconductor chips, then chip identification capability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the chip selection function into multiple segments by using different through-line configurations (first configuration and second configuration) that can be selectively activated. Each configuration serves a specific chip identification purpose, allowing the system to distinguish multiple chips without requiring a complete set of through-lines for every possible chip combination. This segmentation reduces the total number of through-lines needed while maintaining identification capability.
Solution Approach 2:
The patent introduces a temporal dimension to the through-line usage by switching between different through-line configurations over time. Instead of using all through-lines simultaneously for chip identification, the system alternates between first and second configurations, effectively using the time dimension to multiply the identification capability without increasing the spatial number of through-lines.
2Measurement precision
If more through-lines are implemented to designate multiple chips, then chip designation accuracy is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the chip designation process into multiple phases using different through-line configurations. By activating only the necessary through-lines for each specific chip designation task rather than requiring all through-lines to be perfectly aligned simultaneously, the system reduces the cumulative alignment precision requirements while maintaining accurate chip designation.
Solution Approach 2:
The patent makes the through-line configuration dynamic by allowing switching between first and second configurations. This dynamic approach enables the system to adapt the active through-line set to the specific chip being designated, reducing the need for all through-lines to maintain perfect alignment at all times and thereby lowering overall manufacturing precision requirements.
3Adaptability or versatility
If a simple directed cycle configuration is used for through-lines, then the number of distinguishable chip combinations increases, but the arrangement complexity increases
Solution Approach 1:
The patent employs asymmetric through-line arrangements within the directed cycle configuration, where through-lines are positioned at non-uniform intervals or with different orientations. This asymmetry creates unique electrical characteristics for each through-line combination, increasing the number of distinguishable chip combinations without requiring a proportional increase in the total number of through-lines, thereby managing arrangement complexity.
Solution Approach 2:
The patent utilizes periodic switching between different through-line configurations in the directed cycle. By periodically activating different sets of through-lines in a predetermined sequence, the system generates multiple distinguishable chip combinations from a limited physical through-line structure, effectively increasing versatility without proportionally increasing physical arrangement complexity.
Data Source
AI summary
A method is disclosed for selecting a semiconductor chip in a stack of semiconductor chips interconnected by through-lines by receiving selection signals at the first terminals located on a first surface of the semiconductor chip, connecting each first terminal to a selected second terminal located on a second surface of the semiconductor chip where each selected second terminal is not aligned with the first terminal to which it is connected, and generating an internal signal based on a selected one of the received selection signals.