Stacked-Chip Image Sensor Vertical Readout for Focus Bracketing
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Solution Overview
Problem
Conventional imaging systems with stacked-chip image sensors are limited in capturing images at multiple focuses due to shared column and row lines, resulting in reduced frame rates and blurry images of objects at different distances.
Innovation Solution
The implementation of vertical conductive interconnects, such as through-silicon vias, allows for simultaneous readout of multiple pixel rows and columns, coupled with an adjustable lens system that captures a variable focus image bracket at high frame rates, enabling the generation of focused images with multiple image focuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If shared column and row lines are used for reading out image pixel data, then device complexity is reduced, but readout rate and frame rate are limited
Solution Approach 1:
The patent transitions from a planar 2D arrangement of control circuitry to a 3D stacked architecture where control circuitry is positioned vertically beneath the pixel array. This dimensional change enables multiple independent readout paths through vertical interconnects, dramatically increasing readout rate without increasing lateral complexity
Solution Approach 2:
The patent divides the control circuitry into multiple independent segments (row drivers, column drivers, ADCs) that are vertically distributed across different layers. Each segment can operate independently and simultaneously, enabling parallel readout of multiple pixel rows and columns, thus increasing overall productivity
2Device complexity
If conventional single-focus imaging is used, then device complexity is minimized, but image quality for objects at different distances deteriorates
Solution Approach 1:
The patent implements a dynamically adjustable lens system that can change its focal length or focus position in real-time. This allows the imaging system to adapt to objects at different distances, maintaining high image quality across varying object depths without requiring multiple fixed-focus sensors
Solution Approach 2:
The system performs preliminary focus bracketing by capturing multiple images at different focus positions before final image processing. This preliminary action at different focuses allows subsequent computational combination to produce a final image with extended depth of field or selective focus regions
3Manufacturing precision
If multiple image frames at different focuses are captured, then image quality for objects at various distances is improved, but frame rate decreases due to shared readout lines
Solution Approach 1:
The stacked-chip architecture enables continuous high-rate capture of focus bracket images by providing dedicated vertical readout paths that can simultaneously read out multiple pixel rows. This eliminates the bottleneck of shared lateral lines, maintaining high frame rates even when capturing multiple focus planes
Solution Approach 2:
The patent combines multiple pixel row readout paths vertically through the stacked-chip interconnect structure. This merging of readout channels into unified vertical pathways increases bandwidth and enables simultaneous readout of multiple rows, maintaining high frame rates during multi-focus capture
Data Source
AI summary
Imaging systems may be provided with stacked-chip image sensors and adjustable lens systems. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels and processing circuitry. The adjustable lens system may pass light from a scene onto the image pixels at a number of focus positions. The image pixels may capture a focus bracket of image frames at a capture frame rate for light passed by the adjustable lens system at two or more of the focus positions. The processing circuitry may combine a set of image frames in the focus bracket to generate a focused image. The focused image may have one or more portions of the captured scene in focus. The processing circuitry may output the focused image to off-chip image processing circuitry at an output frame rate that is less than the capture frame rate.