Stacked Semiconductor Chip Wiring for Image Shading Reduction
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Solution Overview
Problem
Existing imaging apparatuses with stacked chip configurations experience uneven image quality due to varying properties of electric circuits, leading to shading issues in the resulting images.
Innovation Solution
A semiconductor apparatus with a stack of chips, where a first chip with pixel circuits is arranged in a matrix form and a second chip with electric circuits is also in a matrix form, with specific connections between pixel circuits and electric circuits to reduce the distance between corresponding elements, thereby minimizing property differences and shading effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pixel circuits and electric circuits are connected in a conventional stacked configuration, then the device structure is simple, but the distance between corresponding pixel circuits and electric circuits is large causing property variations and shading
Solution Approach 1:
The patent transitions from a conventional one-to-one vertical stacking configuration to a many-to-one connection architecture where multiple pixel circuits connect to a single electric circuit through intermediate wiring layers. This dimensional reorganization reduces the horizontal distance between pixel circuits and electric circuits, minimizing property variations and shading effects while maintaining manageable device complexity through systematic wiring design.
2Reliability
If the distance between pixel circuits and electric circuits is reduced, then property differences are minimized reducing shading, but the wiring structure becomes more complex
Solution Approach 1:
The patent merges multiple pixel circuits to share common electric circuits through intermediate wiring layers, creating a consolidated connection architecture. This merging approach reduces the overall wiring complexity compared to individual dedicated connections while maintaining short distances between pixel circuits and electric circuits, thereby ensuring signal processing consistency and minimizing shading.
Solution Approach 2:
Each electric circuit is designed to handle signals from multiple pixel circuits, giving it a universal function. This multi-functionality reduces the total number of electric circuits needed and simplifies the wiring structure while maintaining reliable signal processing across all pixel circuits, preventing shading effects.
3Quantity of substance
If a stack of chips with matrix arrangement is used, then integration density is improved, but unevenness in image quality occurs due to varied properties of electric circuits at different positions
Solution Approach 1:
The patent implements local quality optimization by creating distinct connection regions where pixel circuits in different areas of the matrix connect to electric circuits through locally optimized wiring paths. This ensures that each region maintains consistent electrical properties despite the overall matrix arrangement, preventing position-dependent image quality variations while maintaining high integration density.
Data Source
AI summary
A semiconductor apparatus includes a stack of first and second chips each having a plurality of pixel circuits arranged in a matrix form. The pixel circuit of the a-th row and the e1-th column is connected to the electric circuit of the p-th row and the v-th column. The pixel circuit of the a-th row and the f1-th column is connected to the electric circuit of the q-th row and the v-th column. The pixel circuit of the a-th row and the g1-th column is connected to the electric circuit of the r-th row and the v-th column. The pixel circuit of the a-th row and the h1-th column is connected to the electric circuit of the s-th row and the v-th column.