Stacked Semiconductor Chip Package Shared DLL Signal

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Solution Overview

Problem

In dual-die semiconductor packages, the presence of separate DLL circuits on each chip leads to increased power consumption and area occupation due to redundant DC generating circuits, which are necessary for each chip despite sharing the same external clock.

Innovation Solution

A semiconductor chip package configuration where DC generating circuits are centralized on a dedicated DC chip, and DLL clock signals are shared among chips, reducing the need for redundant circuits and optimizing chip area usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate DC generating circuits are provided on each chip in a dual-die package, then each chip can operate independently, but power consumption increases and chip area is wasted due to redundancy

Engineering Contradiction:

Improveindependent chip operationVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent merges the DC generating circuits from multiple chips into a single shared circuit on one chip within the dual-die package. This consolidation eliminates redundant DC generating circuits while maintaining independent operation of each chip through separate DLL circuits and signal paths, thereby reducing overall power consumption without sacrificing operational independence.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared DC generating circuit is designed to serve multiple chips simultaneously, providing universal power generation functionality. The circuit generates DC signals that are distributed to both chips in the dual-die package, allowing a single circuit to perform the function that would otherwise require separate circuits on each chip.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If separate DC generating circuits are provided on each chip, then each chip has complete functionality, but the occupied area increases due to redundant circuits

Engineering Contradiction:

Improvechip functionalityVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines the DC generating circuits into a single shared location on one chip, eliminating the need for redundant circuits on the second chip. This merging reduces the total area occupied by DC generating circuits while maintaining full functionality of both chips through the shared power generation resource.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent extracts the DC generating circuit functionality from both chips and consolidates it into a single dedicated circuit on one chip. This extraction removes the redundant circuitry from the second chip, freeing up area while preserving the essential DC signal generation capability needed for both chips to function.

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If separate DLL circuits are provided on each chip, then each chip can synchronize independently, but power consumption increases due to redundant DLL operation

Engineering Contradiction:

Improveclock synchronizationVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent merges the DLL circuit functionality into a single shared circuit on one chip, while the other chip receives the synchronized clock signal through inter-chip connections. This consolidation eliminates redundant DLL operation and associated power consumption while maintaining proper clock synchronization for both chips through the shared DLL output.

Inventive Principle:

Principle #5Merging (Combining)

4Reliability

If all chips include DC generating circuits, then each chip is self-sufficient, but fabrication productivity decreases due to complex multi-step processes

Engineering Contradiction:

Improvechip self-sufficiencyVSAvoidfabrication productivity

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent combines the DC generating circuit fabrication into a single chip process, eliminating the need for separate DC generating circuit fabrication steps on multiple chips. This merging simplifies the overall fabrication process by reducing the number of steps required while maintaining chip self-sufficiency through the shared DC generation capability.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS8228704B2Stacked semiconductor chip package with shared DLL signal and method for fabricating stacked semiconductor chip package with shared DLL signal

Publication Date: 2012.07.24 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor chip package and a semiconductor chip fabricating method are provided. A semiconductor chip package comprises at least two semiconductor chips having a stacked configuration, the semiconductor chips at least one of: sharing DC signals of DC generating circuits provided by one of the semiconductor chips; and sharing a DLL clock signal of a DLL circuit provided by the semiconductor chip having the DC generating circuits or provided by another semiconductor chip. Power consumption can be reduced, and sharing a DLL clock is valid. In addition, a stabilized DC supply can be guaranteed and an increase for level trimming range and productivity can be improved.