Stacked Memory Chip Wiring With Shield Lines for Low Bit-Line Coupling
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently integrating memory cell arrays and sense amplifiers while minimizing coupling between bit lines and complementary bit lines, which affects signal interference and wire length.
Innovation Solution
The semiconductor memory device employs a stacked chips structure where memory cell arrays and sense amplifiers are positioned on different wafers, with bit lines and complementary bit lines extending in different layers and connected through efficient wire arrangements, including refracted lines and shield lines to reduce coupling and wire length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If bit lines and complementary bit lines are arranged adjacent to each other in a stacked chip structure, then wire length is reduced, but coupling between bit lines and complementary bit lines increases causing signal interference
Solution Approach 1:
The patent introduces a shield line as an intermediary element positioned between bit lines and complementary bit lines. This shield line acts as a mediator that blocks electromagnetic coupling between adjacent bit lines, reducing signal interference while allowing the wires to maintain short lengths in the stacked chip structure.
Solution Approach 2:
The patent utilizes the vertical dimension in stacked chip architecture to arrange bit lines and complementary bit lines in different layers. By positioning these conductors in the vertical dimension rather than only in the planar dimension, the patent reduces coupling while maintaining efficient connections, as the vertical separation reduces electromagnetic interference compared to planar arrangement.
2Device complexity
If memory cell arrays and sense amplifiers are integrated on the same chip, then device complexity is reduced, but coupling between bit lines and complementary bit lines increases
Solution Approach 1:
The patent segments the memory device into multiple stacked chips: a first chip containing memory cell arrays and a second chip containing sense amplifiers. This segmentation separates the functions of data storage and data detection into different physical locations, reducing coupling between bit lines and complementary bit lines while maintaining integrated device operation through vertical stacking.
Solution Approach 2:
The patent introduces shield lines as intermediary elements between bit lines and complementary bit lines in the stacked configuration. These shield lines mediate the electromagnetic field interactions, blocking harmful coupling signals while allowing the segmented architecture to function as an integrated device.
3Object-affected harmful factors
If shield lines are added between bit lines and complementary bit lines, then signal interference is reduced, but device complexity increases
Solution Approach 1:
The patent merges the shield line function with existing bit line structures by positioning shield lines adjacent to bit lines in the same or different layers. This combining approach reduces the need for separate, complex shielding structures while effectively reducing signal interference through the stacked chip architecture.
Data Source
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AI summary
A semiconductor memory device may include a first chip including a first array matrix and a second array matrix adjacent to each other and including memory cells, and a second chip below the first chip, and including sense amplifiers configured to drive the memory cells, where first cell bit lines are in the first array matrix, and second cell bit lines are in the second array matrix, where first bit lines and first complementary bit lines are below the first array matrix, and second bit lines and second complementary bit lines are below the second array matrix, where the first bit lines and the second bit lines are connected to the first cell bit lines and the second cell bit lines, respectively, and where the first complementary bit lines and the second complementary bit lines are connected to the second cell bit lines and first cell bit lines, respectively.