Stacked Chip Module Side Pads for Flatness and Reliable Bonding
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Solution Overview
Problem
The total thickness variation (TTV) of the side surface of a chip module formed by stacking multiple chips is significant, leading to uneven surfaces that adversely affect the welding strength between pads and peripheral devices, thereby reducing the performance of semiconductor structures.
Innovation Solution
A method involving the planarization of scribe line regions after chip module formation to expose power supply wiring layers, which extends from the element region to the scribe line region, ensuring flatness and avoiding damage to the element region during planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple chips are stacked to form a chip module, then chip integration and density are improved, but the total thickness variation of the side surface increases causing uneven surfaces
Solution Approach 1:
The power supply wiring layer is extended to the scribe line region in advance during chip fabrication, before stacking. This preliminary action ensures that when planarization is performed after stacking, the wiring layer is already positioned to be exposed, eliminating the need for deep planarization that would cause TTV issues
Solution Approach 2:
The power supply wiring layer is extended from the element region into the scribe line region, utilizing the lateral dimension to position the wiring layer such that it becomes exposed after minimal planarization, thereby reducing the planarization depth required
2Manufacturing precision
If planarization is performed to improve side surface flatness, then welding strength is improved, but the element region may be damaged if planarization removes too much material
Solution Approach 1:
The power supply wiring layer is extended to the scribe line region before stacking, so that after stacking and planarization, the wiring layer is automatically exposed without requiring removal of the element region. This preliminary positioning protects the element region from damage
Solution Approach 2:
The extended power supply wiring layer in the scribe line region serves as an intermediary structure that can be exposed through planarization without affecting the element region. It acts as a buffer zone that allows planarization to proceed safely
3Manufacturing precision
If the power supply wiring layer extends to the scribe line region, then planarization can expose the wiring layer without damaging the element region, but the chip structure becomes more complex
Solution Approach 1:
The scribe line region, which traditionally serves only for chip separation, is repurposed to also accommodate the extended power supply wiring layer. This multi-functional use of the scribe line region avoids adding extra structural complexity while achieving the desired planarization safety
Data Source
AI summary
Embodiments provide a fabricating method, a semiconductor structure, and a semiconductor device. The method includes: providing a plurality of chips, each of the chips includes an element region and a scribe line region arranged in a first direction; stacking the chips to form a chip module, where a stacking direction of the chips is a second direction perpendicular to the first direction, the element regions of the chips are overlapped with each other, and the scribe line regions of the chips are overlapped with each other; planarizing a side surface of each of the scribe line regions distant from the element region after the chip module is formed, to remove at least part of the scribe line regions and expose the power supply wiring layer; and forming a pad on the side surface planarized, where the pad is connected to the power supply wiring layer.